Richard J Nathan

US Patent:

6528351, Mar 4, 2003

Filed:

Sep 24, 2001

Appl. No.:

09/963337

Inventors:

Richard J. Nathan - Morgan Hill CA
William H. Shepherd - Placitas NM

Assignee:

JigSaw tek, Inc. - Gilroy CA

International Classification:

H01L 2144

US Classification:

438118, 438124, 438126, 438127

Abstract:

One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system. When a single integrated circuit chip is to be embedded in a substrate, the invention makes possible the simultaneous manufacture of a plurality of such packaged integrated circuit chips in a single large substrate using standard semiconductor or printed circuit photolithographic and processing techniques and then singulating the large substrate into a plurality of smaller substrates, each containing a single integrated circuit chip. Likewise, when more than one integrated circuit chip is embedded in a substrate, a plurality of such structures can be manufactured in a single large substrate and then singulated into a plurality of smaller substrates, each containing more than one integrated circuit chips.

US Patent:

6903458, Jun 7, 2005

Filed:

Jun 20, 2002

Appl. No.:

10/177841

Inventors:

Richard J. Nathan - Morgan Hill CA, US

International Classification:

H01L023/488
H05K007/02

US Classification:

257737, 257772, 257777, 257778, 361783

Abstract:

A carrier for an integrated chip is embedded into a substrate, so that stresses due to thermal expansion are uniformly distributed over an interface between the substrate and the carrier (hereinafter “embedded carrier”). Such an embedded carrier may be formed of a material having a coefficient of thermal expansion similar or identical to the coefficient of thermal expansion of an integrated circuit chip to be mounted thereon, so as to eliminate stresses (due to thermal expansion) at joints between the carrier and the integrated circuit chip. The just-described joints may be formed by any method well known in the art, e. g. flip-chip bonding. Such packaging of one or more integrated circuit chip(s) eliminates reliability issues associated with conventional flip chip bonded components, which are caused by, for example, concentration of stresses in conventional solder ball interconnections between a chip and a substrate.

US Patent:

20030057544, Mar 27, 2003

Filed:

Mar 12, 2002

Appl. No.:

10/097363

Inventors:

Richard Nathan - Morgan Hill CA, US
William Shepherd - Placitas NM, US

International Classification:

H01L021/48
H01L023/48
H01L029/40

US Classification:

257/700000, 257/692000, 257/778000, 438/108000, 257/782000, 257/786000, 438/612000, 438/618000

Abstract:

A monolithic integrated structure including one or more packaged components such as integrated circuits, discreet components, LED's, photocouplers and the like is formed by placing electrically conductive lands on one surface of each packaged component, and then placing one or more packaged components into a substrate such that the surface of each packaged component containing the electrically conductive lands is visible and substantially coplanar with the top surface of the substrate. An electrically conductive layer is then formed over the top surface of the substrate, on the visible surfaces of each of the packaged components and on the electrically conductive lands contained thereon. The electrically conductive layer is then patterned using standard photolithographic techniques known in the semiconductor and printed circuit processing arts to form an electrical interconnect which connects the packaged components into a desired electrical circuit. The resulting structure thus is low cost yielding either packaged single integrated circuit structures or multi-package structures which either form an electronic system or which are capable of being electrically interconnected with other such structures to form an entire electronic system.

US Patent:

20030059976, Mar 27, 2003

Filed:

Mar 12, 2002

Appl. No.:

10/098021

Inventors:

Richard Nathan - Morgan Hill CA, US
William Shepherd - Placitas NM, US

International Classification:

H01L021/48

US Classification:

438/106000

Abstract:

One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system. When a single integrated circuit chip is to be embedded in a substrate, the invention makes possible the simultaneous manufacture of a plurality of such packaged integrated circuit chips in a single large substrate using standard semiconductor or printed circuit photolithographic and processing techniques and then singulating the large substrate into a plurality of smaller substrates, each containing a single integrated circuit chip. Likewise, when more than one integrated circuit chip is embedded in a substrate, a plurality of such structures can be manufactured in a single large substrate and then singulated into a plurality of smaller substrates, each containing more than one integrated circuit chip. A plurality of substrates with embedded integrated circuit chips can be stacked to form a composite multichip, multi-layered structure. Additional chips, packaged or unpackaged, can be placed on the top of this composite structure.

US Patent:

20030102572, Jun 5, 2003

Filed:

Sep 13, 2001

Appl. No.:

09/953005

Inventors:

Richard Nathan - Morgan Hill CA, US
William Shepherd - Placitas NM, US

International Classification:

H01L023/48
H01L023/52
H01L029/40

US Classification:

257/780000

Abstract:

A monolithic integrated structure including one or more packaged components such as integrated circuits, discreet components, LED's, photocouplers and the like is formed by placing electrically conductive lands on one surface of each packaged component, and then placing one or more packaged components into a substrate such that the surface of each packaged component containing the electrically conductive lands is visible and substantially coplanar with the top surface of the substrate. An electrically conductive layer is then formed over the top surface of the substrate, on the visible surfaces of each of the packaged components and on the electrically conductive lands contained thereon. The electrically conductive layer is then patterned using standard photolithographic techniques known in the semiconductor and printed circuit processing arts to form an electrical interconnect which connects the packaged components into a desired electrical circuit. The resulting structure thus is low cost yielding either packaged single integrated circuit structures or multi-package structures which either form an electronic system or which are capable of being electrically interconnected with other such structures to form an entire electronic system.

US Patent:

20030153119, Aug 14, 2003

Filed:

Feb 14, 2002

Appl. No.:

10/077211

Inventors:

Richard Nathan - Morgan Hill CA, US
Dale Means - Fremont CA, US

International Classification:

H01L021/44

US Classification:

438/106000

Abstract:

An integrated circuit package includes at least one semiconductor die embedded in a substrate made of a heat deformable material such as plastic or a combination of plastics. The at least one die is embedded so that the top surface of the at least one die, which contains a plurality of bonding pads, is exposed, and, in certain embodiments, substantially coplanar with the top surface of the substrate. A layer of conductive material is then formed on the top surface of the substrate and on the top surfaces(s) of at least one semiconductor die. This layer is formed into a plurality of electrically conductive paths each path beginning at a selected bonding pad and terminating in an electrically conductive land on the top surface of the substrate. Electrical connection is then made between the at least one die and external circuitry by placing the structure on a printed circuit board, for example, with electrically conductive balls between the electrically conductive lands on the substrate and adjacent electrical contacts on the printed circuit board. If desired, a protective coating can be formed over the at least one semiconductor die or over the combination of the at least one semiconductor die and the substrate to protect the surface of the at least one semiconductor die.

US Patent:

57264821, Mar 10, 1998

Filed:

Oct 7, 1994

Appl. No.:

8/319906

Inventors:

Richard J. Nathan - Morgan Hill CA
James J. D. Lan - Fremont CA
Steve S. Chiang - Saratoga CA
Paul Y. F. Wu - San Jose CA
Robert Osann - Los Altos CA

Assignee:

Prolinx Labs Corporation - San Jose CA

International Classification:

H01L 2900

US Classification:

257529

Abstract:

A device-under-test card includes a matrix of fuses and/or antifuses formed as part of a multi-layered structure. The matrix of fuses and/or antifuses can be electrically programmed to connect any one of first electrical contacts to any one of second electrical contacts and so allows the device-under-test card to act as a junction between burn-in board traces couplable to signal drivers and/or receivers and burn-in board traces couplable to terminals of a device-under-test. The device-under-test card also includes a discrete resistor or alternatively a resistor ladder that permits a terminal of a device-under-test to be coupled to a power or ground terminal or to any combination of resistances including a short, in addition or as an alternative to any one of various signal drivers and/or receivers.

US Patent:

55724094, Nov 5, 1996

Filed:

Oct 7, 1994

Appl. No.:

8/319860

Inventors:

Richard J. Nathan - Morgan Hill CA
James J. D. Lan - Fremont CA
Steve S. Chiang - Saratoga CA

Assignee:

Prolinx Labs Corporation - San Jose CA

International Classification:

H05K 706
H01R 909

US Classification:

361806

Abstract:

Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable socket adapter in one embodiment. The socket adapter can be used for interconnecting an electronic component having terminals in a first configuration to electrical contacts in printed circuit board.