Richard L Nicholas

US Patent:

7275199, Sep 25, 2007

Filed:

Aug 5, 2004

Appl. No.:

10/912483

Inventors:

Robert Christopher Dixon - Austin TX, US
Richard Nicholas - Pflugerville TX, US
Kirk Edward Morrow - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/52

US Classification:

714763, 711 2, 711 5, 714773

Abstract:

A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.

US Patent:

7328312, Feb 5, 2008

Filed:

Feb 3, 2005

Appl. No.:

11/050295

Inventors:

Bernard Charles Drerup - Austin TX, US
Richard Nicholas - Pflugerville TX, US
Barry Joe Wolford - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/28
G06F 12/00

US Classification:

711137, 711154

Abstract:

A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. The master generates a continue bus signal that indicates a new or a continued request. The master generates a prefetch bus signal that indicates an amount to prefetch including no prefetching. The master includes a mechanism for continuing a sequence of reads allowing prefetching until a request is made indicating a prefetch amount of zero.

US Patent:

7366811, Apr 29, 2008

Filed:

Dec 23, 2004

Appl. No.:

11/021534

Inventors:

Richard Nicholas - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/362

US Classification:

710118, 710113

Abstract:

A circuit arrangement, program product and method for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the sequence for a second group of devices, granting access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.

US Patent:

7487276, Feb 3, 2009

Filed:

Mar 14, 2008

Appl. No.:

12/048772

Inventors:

Richard Nicholas - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/362

US Classification:

710118, 710113

Abstract:

A circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the sequence for a second group of devices, granting access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.

US Patent:

7490201, Feb 10, 2009

Filed:

Nov 26, 2007

Appl. No.:

11/944644

Inventors:

Bernard Charles Drerup - Austin TX, US
Richard Nicholas - Pflugerville TX, US
Barry Joe Wolford - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/28
G06F 12/00

US Classification:

711137, 711100, 711154, 710 56

Abstract:

A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. The master generates a continue bus signal that indicates a new or a continued request. The master generates a prefetch bus signal that indicates an amount to prefetch including no prefetching. The master includes a mechanism for continuing a sequence of reads allowing prefetching until a request is made indicating a prefetch amount of zero.

US Patent:

7523228, Apr 21, 2009

Filed:

Sep 18, 2006

Appl. No.:

11/532562

Inventors:

Giora Biran - Zichron-Yaakov, IL
Luis E. De la Torre - Austin TX, US
Bernard C. Drerup - Austin TX, US
Jyoti Gupta - Austin TX, US
Richard Nicholas - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/28
G06F 3/00

US Classification:

710 22, 710 24, 710 28, 710 36, 710 52, 710 57

Abstract:

A direct memory access (DMA) device is structured as a loosely coupled DMA engine (DE) and a bus engine (BE). The DE breaks the programmed data block moves into separate transactions, interprets the scatter/gather descriptors, and arbitrates among channels. The DE and BE use a combined read-write (RW) command that can be queued between the DE and the BE. The bus engine (BE) has two read queues and a write queue. The first read queue is for “new reads” and the second read queue is for “old reads,” which are reads that have been retried on the bus at least once. The BE gives absolute priority to new reads, and still avoids deadlock situations.

US Patent:

7603490, Oct 13, 2009

Filed:

Jan 10, 2007

Appl. No.:

11/621776

Inventors:

Giora Biran - Zichron-Yaakov, IL
Luis E. De la Torre - Austin TX, US
Bernard C. Drerup - Austin TX, US
Jyoti Gupta - Austin TX, US
Richard Nicholas - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/28
G06F 13/32

US Classification:

710 23, 710 24

Abstract:

A direct memory access (DMA) device includes a barrier and interrupt mechanism that allows interrupt and mailbox operations to occur in such a way that ensures correct operation, but still allows for high performance out-of-order data moves to occur whenever possible. Certain descriptors are defined to be “barrier descriptors. ” When the DMA device encounters a barrier descriptor, it ensures that all of the previous descriptors complete before the barrier descriptor completes. The DMA device further ensures that any interrupt generated by a barrier descriptor will not assert until the data move associated with the barrier descriptor completes. The DMA controller only permits interrupts to be generated by barrier descriptors. The barrier descriptor concept also allows software to embed mailbox completion messages into the scatter/gather linked list of descriptors.

US Patent:

7620749, Nov 17, 2009

Filed:

Jan 10, 2007

Appl. No.:

11/621789

Inventors:

Giora Biran - Zichron-Yaakov, IL
Luis E. De la Torre - Austin TX, US
Bernard C. Drerup - Austin TX, US
Jyoti Gupta - Austin TX, US
Richard Nicholas - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/28

US Classification:

710 22, 712207

Abstract:

A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, the DMA engine prefetches descriptors based on the assumption that they are sequential in memory and discards any descriptors that are found to violate this assumption. The DMA engine seeks to keep the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. The bus engine fetches these descriptors from system memory and writes them to the prefetch buffer. The DMA engine may also use an aggressive prefetch where the bus engine requests the maximum number of descriptors that the buffer will support whenever there is any space in the descriptor prefetch buffer. The DMA device discards any remaining descriptors that cannot be stored.