Richard Edward Nicholas

US Patent:

7836257, Nov 16, 2010

Filed:

Dec 19, 2007

Appl. No.:

11/959804

Inventors:

Robert John Dorsey - Durham NC, US
Jason Alan Cox - Raleigh NC, US
Hien Minh Le - Cedar Park TX, US
Richard Nicholas - Round Rock TX, US
Eric Francis Robinson - Raleigh NC, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corpation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711133, 711118, 711119, 711124, 711134, 711136, 711141, 711159, 711160

Abstract:

A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.