Richard J Partridge

US Patent:

41575865, Jun 5, 1979

Filed:

May 5, 1977

Appl. No.:

5/794323

Inventors:

Patrick M. Gannon - Poughkeepsie NY
Julius D. Jones - Unionvale NY
Dale M. Junod - Highland NY
Richard L. Partridge - Wappingers Falls NY
Thomas R. Wright - Shokan NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 702

US Classification:

364200

Abstract:

This specification relates to performance of partial store operation in a hierarchical memory system which has a buffer store interposed between a processor interrogating the memory system and the main memory of the memory system. Such a partial store operation can be performed on a word of data in the main memory using the buffer store copy of that word of data. The copy of the word of data is read out of the buffer store into a register where it is modified to form a new word by replacing one or more but not all of the bytes in the word of data with bytes supplied by the processor. The new word is then placed in the main memory by performing a full store operation. The problem with performing a partial store operation in this manner is that the copy of the word of data in the buffer store may not be up-to-date. A technique is provided to eliminate the possibility of this old data being rewritten back into the main memory.

US Patent:

41422341, Feb 27, 1979

Filed:

Nov 28, 1977

Appl. No.:

5/855485

Inventors:

Bradford M. Bean - New Paltz NY
Keith N. Langston - Ulster Park NY
Richard L. Partridge - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300
G06F 1516

US Classification:

364200

Abstract:

The disclosed embodiments filter out many unnecessary interrogations of the cache directories of processors in a multiprocessor (MP) system, thereby reducing the required size of the buffer invalidation address stack (BIAS) with each associated processor, and increasing the efficiency of each processor by allowing it to access its cache during the machine cycles which in prior MP's had been required for invalidation interrogation. Invalidation interrogation of each remote processor cache directory may be done when each channel or processor generates a store request to a shared main storage. A filter memory is provided with each BIAS in the MP. The filter memory records the cache block address in each invalidation request transferred to its associated BIAS. The filter memory deletes an address when it is deleted from the cache directory and retains the most recent cache access requests. The filter memory may have one or more registers, or be an array.