Richard J Petschauer

US Patent:

7386988, Jun 17, 2008

Filed:

Mar 9, 2004

Appl. No.:

10/796516

Inventors:

Richard J. Petschauer - Edina MN, US

International Classification:

F25B 49/00
B01F 3/02

US Classification:

621766, 621761, 236 44 R

Abstract:

A humidity control system having an outside temperature humidity compensator circuit responsively coupled to an outside temperature sensing circuit and capable of responding to sensed inside humidity levels to provide control signals to a humidity controller to automatically adjust the target in-room humidity produced by a controller as a function of sensed changes in outside temperature is described. The compensator circuit provides two variables to allow control of both the level of humidity at a specified temperature and the rate of humidity change with changes in outside temperature, and provides a means to limit the highest humidity level that is independent of the controlling variables. Switching is shown to allow the compensator circuit to be switched out of operation and to allow it to be momentarily bypassed.

US Patent:

55965067, Jan 21, 1997

Filed:

Feb 9, 1995

Appl. No.:

8/385850

Inventors:

Richard J. Petschauer - Edina MN
Roland D. Rothenberger - Poway CA
Paul G. Tumms - Fridley MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

H04B 332

US Classification:

364491

Abstract:

In one method according to the present invention, an integrated circuit chip is fabricated by the following steps: 1) providing a trial layout in the chip for a victim net and a set of aggressor nets which have segments that lie next to the victim net; 2) assigning to the trial layout of the victim net, the parameters of--a line capacitance, a line resistance, and a driver output resistance; and assigning to the trial layout of each aggressor net, the parameters of--a coupling capacitance to the victim net, and a voltage transition; 3) estimating, for each aggressor net, a respective peak crosstalk voltage V. sub. p which the aggressor net couples into the victim net as a function V. sub. p =K(e. sup. -X -e. sup. -Y) where K, X, and Y are products of said parameters; 4) modifying said trial layout and repeating the assigning and estimating steps until a summation of the estimated peak crosstalk voltages in the victim net is within an acceptable level; and, 5) building the chip with the modified layout for which the summation is within the acceptable level.

US Patent:

55351336, Jul 9, 1996

Filed:

Feb 9, 1995

Appl. No.:

8/385848

Inventors:

Richard J. Petschauer - Edina MN
Roland D. Rothenberger - Poway CA
Paul G. Tumms - Fridley MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1750
G06F 1710

US Classification:

364489

Abstract:

Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the "victim net") has several segments that respectively lie next to several other nets (called "aggressor nets"), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the preset invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of a table. In one embodiment, the table estimates the peak crosstalk voltage per unit length which is coupled by each aggressor net separately; and in each repetitive cycle, the table is read separately for each aggressor net. In another embodiment, the table estimates the average peak crosstalk voltage per unit length which all of the aggressor nets together couple into the victim net; and in each repetitive cycle, the table is read only a single time.

US Patent:

53612329, Nov 1, 1994

Filed:

Nov 18, 1992

Appl. No.:

7/978128

Inventors:

Richard J. Petschauer - Edina MN
Paul G. Johnson - Brooklyn Park MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01R 3128

US Classification:

365201

Abstract:

An apparatus and method for improving the testability of six cell CMOS SRAM circuits. The technique involves adding transistors and the ability to effectively disable the precharge circuitry during the test mode. This makes the pull up transistors the only current source for switching the memory cell. An open or weak pull up transistor, which would appear as an intermittent soft failure under operational conditions because of the current sourcing of the precharge circuitry, becomes a hard stuck-at failure under the test conditions. Because the precharge circuitry is disabled for all memory cells, a slower memory clock speed is used for memory cycling during the test mode.

US Patent:

52668908, Nov 30, 1993

Filed:

Jun 26, 1992

Appl. No.:

7/905596

Inventors:

Cevat Kumbasar - Carlsbad CA
Jonathan A. Levi - Fallbrook CA
Richard J. Petschauer - Edina MN
Roy R. Shanks - San Diego CA
Steven S. Wei - San Diego CA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01R 3100

US Classification:

324158R

Abstract:

An integrated circuit test wafer quickly detects A-C defects in any process by which the wafer is fabricated. This test wafer includes a semiconductor substrate having a major surface, and a diagnostic circuit that is repeatedly integrated over most of the wafer's surface. Each diagnostic circuit includes: a) a plurality of ring oscillators which generate respective cyclic output signals; b) an addressing circuit that receives external input signals and in response selects an output signal from any particular ring oscillator of the plurality; c) a timing circuit that generates a timing signal with a certain time period; and, d) a counting circuit that counts the number of cycles that occur in the selected output signal during the time period and provides that number as an output. By comparing the relative or absolute speeds of all of the ring oscillators, a ring oscillator with an A-C defect is detected; and, a defective ring oscillator can then be analyzed under an E-beam microscope to determine the defects cause. Preferably, the ring oscillators occupy at least 90% of the test wafers surface so that A-C defects are detected even when they are sparsely distributed on the test wafer.

US Patent:

48993115, Feb 6, 1990

Filed:

Aug 29, 1988

Appl. No.:

7/237470

Inventors:

Richard J. Petschauer - Edina MN
Robert J. Bergman - Roseville MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G11C 700

US Classification:

36518906

Abstract:

A sense amplifier is provided for a bipolar random access memory that has memory cells arranged in a column and a pair of bit lines for said column of memory cells. A first bipolar transistor has its collector-emitter path coupled to one of the bit lines of a pair, and a base coupled through a diode means to the second bit line. A second bipolar transistor has its collector-emitter path coupled to the second bit line and its base coupled through a second diode to the first bit line. The collectors of both of the bipolar transistors are coupled to provide an output signal. Resistors are coupled to a pulse source and to both of the bases of the bipolar transistors. A current sink is coupled to both of the select bit lines. The diode means are connected so as to be forward biased when the base-emitter junction of the transistor to which the diode means is coupled is also forward biased.

US Patent:

39990516, Dec 21, 1976

Filed:

Mar 28, 1975

Appl. No.:

5/563419

Inventors:

Richard J. Petschauer - Edina MN

Assignee:

Sperry Rand Corporation - New York NY

International Classification:

G06F 1112
G11C 2900

US Classification:

235153AK

Abstract:

A maintenance procedure comprising a method of and an apparatus for storing information identifying the location of one or more defective bits, i. e. , a defective memory element, a defective storage device or a failure, in a single-error-correcting semiconductor main storage unit (MSU) comprised of a plurality of large scale integrated (LSI) bit planes. The method utilizes an error logging store (ELS) comprised of 128 word-group-associated memory registers, each memory register storing 1 tag bit and 6 syndrome bits. Upon determination of a single bit error during the readout of a word from the MSU, stored in the ELS are: (1) a tag bit that when set signifies that a defective bit has been determined to be in the one associated word group; and, (2) a group of 6 syndrome bits that identifies that one of the 45, 1024-bit planes of the one associated word group that contains the defective bit. A defective device counter (DDC) counts the set tag bits in the ELS and is utilized by the machine operator to schedule preventative maintenance of the MSU by replacing the defective bit planes. By statistically determining the number of allowable failures, i. e.

US Patent:

55555063, Sep 10, 1996

Filed:

Feb 9, 1995

Appl. No.:

8/385849

Inventors:

Richard J. Petschauer - Edina MN
Roland D. Rothenberger - Poway CA
Paul G. Tumms - Fridley MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1750
G06F 1710

US Classification:

364491

Abstract:

Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the "victim net") has several segments that respectively lie next to several other nets (called "aggressor nets"), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the present invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of an equation. In one embodiment, the equation estimates the mean crosstalk voltage which is coupled by each aggressor net separately; and in each repetitive cycle, the estimation is made separately for each aggressor net. In another embodiment, a different equation estimated the total mean crosstalk voltage which all of the aggressor nets together couple into the victim net; and in each repetitive cycle, this estimation is made only a single time.