Richard A Powers

US Patent:

7386688, Jun 10, 2008

Filed:

Jul 29, 2004

Appl. No.:

10/902340

Inventors:

Larry N. McMahan - Fremont CA, US
Dong Wei - Granite Bay CA, US
Richard Dickert Powers - Highland Village TX, US
Arad Rostampour - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00

US Classification:

711153, 711152

Abstract:

Information objects and system firmware for a processor in a partitionable computing system are disclosed. One object comprises information corresponding to components of the computer system. The information comprises entries defining an address and a size for registers normally accessible to other partitions. The registers are capable of defining an address area such that in use the processor is arranged to permit other partitions to access at least one address area defined by the at least one register and to deny other partitions access to address areas other than the at least one accessible address area.

US Patent:

56403887, Jun 17, 1997

Filed:

Dec 21, 1995

Appl. No.:

8/576637

Inventors:

Douglas F. Woodhead - Lawrenceville GA
Maynard D. Hammond - Lawrenceville GA
Richard A. Powers - Cumming GA
Paul Rimas Zalkauskas - Cumming GA

Assignee:

Scientific-Atlanta, Inc. - Norcross GA

International Classification:

H04L 1256

US Classification:

370468

Abstract:

In a system that transmits packets containing timestamps and information from a transmission site to a reception site at a transmission bit rate the packets may experience jitter, i. e. variable delay, during transmission. In such a case, the packets are temporally shifted relative to the timestamps and to other packets. Where the timestamp values are inserted into selected packets prior to transmission and that timestamp represent the value of the transmission site clock, the method and apparatus of the present invention substantially removes the jitter and adjusts the timestamp values prior to reception of the packets at the reception site. The present invention achieves this goal by receiving the packets at an intermediate site that has a local clock operates at a nominal frequency substantially equal to the nominal frequency of the transmission site clock and uses that clock as a jitter-free clock to correct the packets. The packets are stored in a buffer at the intermediate site and output from the buffer at a controlled rate to maintain a substantially constant average transit time of packets through the buffer. Before the packets are output for reception at the reception site the timestamps of selected packets are modified to reflect the new temporal relationship between packets due to the controlled rate of output from the intermediate site.