Richard A Rasmussen

US Patent:

6806750, Oct 19, 2004

Filed:

Apr 26, 2002

Appl. No.:

10/133707

Inventors:

Richard Robert Rasmussen - Fremont CA
Benjamin Clyde Buchanan - Duluth GA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03L 706

US Classification:

327156, 327159, 327161

Abstract:

A method for clock deskewing using a continuously calibrated delay element in a phase-locked loop is provided that includes receiving a feedback signal. A skew select signal is received. The feedback signal is delayed based on the skew select signal to generate a delay output signal. The delay output signal is provided to a phase detector. An external clock signal and the delay output signal are received at the phase detector. A phase detector signal is generated based on the external clock signal and the delay output signal. A skewed clock signal and the feedback signal are generated based on the phase detector signal.

US Patent:

7724044, May 25, 2010

Filed:

Jul 23, 2008

Appl. No.:

12/178342

Inventors:

Richard R. Rasmussen - Fremont CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 17/00
G06F 1/08

US Classification:

327 99, 327 34, 327298, 327299

Abstract:

A digital signal multiplexor and multiplexing method are provided with which switching between different input signals is achieved without producing glitches in the output signal, even in the event of one or more of the input signals stopping and starting at unknown times.

US Patent:

59054123, May 18, 1999

Filed:

May 21, 1997

Appl. No.:

8/861268

Inventors:

Richard R. Rasmussen - Fremont CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03B5/24;5/04

US Classification:

331 57

Abstract:

A current controlled oscillator circuit comprising a "variable-ratio current mirror", for providing a variable output current that varies in response to process. The "variable-ratio current mirror" having a reference MOS transistor and a mirrored MOS transistor, and the reference MOS transistor has a greater predetermined channel length than the channel length of the mirrored MOS transistor. A second current mirror is coupled to the "variable-ratio current mirror" to provide a control current that decreases in response to an increase in the variable output current of the "variable-ratio current mirror. " A multi-stage ring oscillator having a plurality of series-connected inverter stages is responsive to the control current of said second current mirror for controlling the frequency of oscillation of said multi-stage ring oscillator.

US Patent:

55613985, Oct 1, 1996

Filed:

May 16, 1995

Appl. No.:

8/442564

Inventors:

Richard R. Rasmussen - Fremont CA

Assignee:

National Semiconductor Corporation - Santo Clara CA

International Classification:

H03B 512
H03L 7099

US Classification:

331 36C

Abstract:

A differential delay stage for a ring oscillator utilizes a resonant circuit formed by an inductor and a capacitor consisting of two varactor diodes connected back-to-back. A common cathode connection is connected to a variable voltage source to vary the capacitance of the diodes. Other forms of capacitors may replace the varactor diodes. Varying the capacitance value varies the resulting oscillation frequency of the ring oscillator. When several delay stages, each incorporating the resonant circuit, are connected together in a ring, the net effect is to allow only a signal at the resonant frequency of the resonant circuits to propagate around the ring. Other oscillator circuits employing a resonant circuit are disclosed.

US Patent:

52316360, Jul 27, 1993

Filed:

Sep 13, 1991

Appl. No.:

7/759469

Inventors:

Richard R. Rasmussen - Fremont CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H04J 300

US Classification:

3701001

Abstract:

Circuit and method of glitchless switching between asynchronous data inputs to a digital multiplexer (MUX) by maintaining and conditioning the width of the clock pulse corresponding to a first data input signal so that an output pulse is produced having a pulse width that is never narrower than the narrowest of input signals, i. e. , does not produce a narrow-pulse glitch. The circuit comprises select inputs in parallel to both a MUX via a select latch device and to an edge detector having an output pulse triggering a synchronization assembly. The synchronization assembly freezes the output in the last state received from the multiplexer. The select input edge detector freezes the original D0 input at a high state until the new input D1 is cleared through the synchronization assembly.

US Patent:

48765198, Oct 24, 1989

Filed:

Jan 23, 1989

Appl. No.:

7/299768

Inventors:

Craig M. Davis - Santa Clara CA
Richard R. Rasmussen - Fremont CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03B 100

US Classification:

331 57

Abstract:

An emitter-coupled logic (ECL) gate configuration is provided that allows variations in the bias current for controlling propagation delay. The emitter coupled logic circuitry includes a plurality of input transistors having commonly-coupled emitters. The collector of each input transistor is connected to receive a control voltage. A current source is connected between the commonly-coupled emitters and ground. Circuitry, preferably a variable resistance, is connected between the collectors of the input transistors and a supply voltage. A bias voltage controls the charging current provided to the collectors of the ECL input transistors.

US Patent:

50619071, Oct 29, 1991

Filed:

Jan 17, 1991

Appl. No.:

7/642677

Inventors:

Richard R. Rasmussen - Fremont CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03B 100

US Classification:

331 57

Abstract:

The present invention provides a high frequency CMOS voltage controlled oscillator circuit with gain constant and duty cycle compensation. The voltage controlled oscillator circuit includes a multi-stage ring oscillator that includes a plurality of series-connected inverter stages comprising N-channel and P-channel transistors. The ring oscillator responds to a control current signal for controlling the frequency of oscillation of the ring oscillator. A voltage-to-current converter converts a tuning voltage input signal to a corresponding output current signal that is independent of the channel strength of the N-channel and P-channel transistors. Process compensation circuitry responds to the tuning voltage input signal to provide a current dump output signal corresponding to the channel strength of the P-channel and N-channel transistors. Trip-point compensation circuit provides a net ring current signal as the current control signal to the ring oscillator. The net ring current signal represents the difference between the output current signal and the current dump output signal and responds to the balance between the output buffer trip point and a ring oscillator dummy stage.