Richard J Reeves

US Patent:

7016213, Mar 21, 2006

Filed:

May 10, 2004

Appl. No.:

10/842297

Inventors:

Richard W. Reeves - Westboro MA, US
Ross V. La Fetra - Sunnyvale CA, US
Paul C. Miranda - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 5/06

US Classification:

365 63, 365233, 710 22

Abstract:

A host is coupled to a serially connected chain of memory modules. In one embodiment, a method for initializing the host and each of memory modules includes the host transmitting a first synchronization pattern and a second synchronization pattern downstream in response to a reset condition. The method also includes each memory module in the serially connected chain of memory modules receiving and forwarding the first and the second synchronization pattern. Each memory module receives and forwards the first and the second synchronization pattern. Further, the method includes the host transmitting a plurality of NOP packets downstream in response to transmitting the second synchronization pattern. Lastly, the method includes a portion of the memory modules injecting and transmitting NOP packets upstream in response to receiving the second synchronization pattern from downstream.

US Patent:

7103703, Sep 5, 2006

Filed:

Jun 14, 2004

Appl. No.:

10/865836

Inventors:

Richard W. Reeves - Westboro MA, US
Austen John Hypher - Newton MA, US
David John Workman - Westborough MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 13/00
G06F 13/42

US Classification:

710312, 710315, 713400

Abstract:

Duplicate PCI bridge devices are configured for synchronous initializations based on shared initialization signals. A first of the PCI bridge devices is configured to rely on bus arbitration performed by the second PCI bridge device. The first PCI bridge device also is configured for modifying an address of a data transaction received via a PCI bus, and forwarding the data transaction with the modified address to the second PCI bridge device via a link distinct from the PCI bus.

US Patent:

7256627, Aug 14, 2007

Filed:

Jan 13, 2005

Appl. No.:

11/033755

Inventors:

Gerald Robert Talbot - Concord MA, US
Richard W. Reeves - Westboro MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03L 7/00

US Classification:

327141, 327146, 327151

Abstract:

A phase alignment circuit having a phase selection circuit, a synchronizer, and a counter form a feedback loop for aligning a local clock signal with a received reference clock of a synchronous communications system. The phase selection circuit is configured for outputting the local clock signal as a phase-adjusted local clock having a selected phase based on a phase selection value specified by the counter. The synchronizer is configured for digitally sampling the received reference clock relative to the phase-adjusted local clock, and outputting a digital phase bit identifying whether the phase-adjusted local clock has a later phase relative to the received reference clock. The counter selectively increments or decrements a counted value based on the digital phase bit, and outputs to the phase selection circuit a prescribed number of most significant bits from the counted value as the phase selection value.

US Patent:

7257654, Aug 14, 2007

Filed:

Nov 9, 2004

Appl. No.:

10/983646

Inventors:

Richard W. Reeves - Westboro MA, US
Austen John Hypher - Newton MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 13/30
G06F 13/36

US Classification:

710104, 710306, 700 26, 326 38

Abstract:

An integrated device (e. g. , an integrated PCI bridge device), having configuration registers for storing configuration values, device logic for generating internal state values based on the configuration values, and a JTAG interface configured for receiving a serial input stream and outputting a serial output stream, further includes write logic and debug read logic. The write logic is configured for writing selected portions of the serial input stream into respective selected ones of the configuration registers, based on a detected input indicating a JTAG-based override. The debug read logic is configured, in response to a detected debug mode, for outputting selected internal state values for the serial output stream, based on selection values from the serial input stream and having been stored in a prescribed at least one of the selected configuration registers.

US Patent:

8575972, Nov 5, 2013

Filed:

Mar 23, 2009

Appl. No.:

12/409228

Inventors:

Richard W. Reeves - Westborough MA, US
Spencer M. Gold - Pepperell MA, US
Steven J. Kommrusch - Fort Collins CO, US
Anwar P. Kashem - Cambridge MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03B 21/00
H03K 3/00

US Classification:

327105, 327107, 327291, 327298

Abstract:

A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.

US Patent:

7269679, Sep 11, 2007

Filed:

Jun 14, 2005

Appl. No.:

11/151317

Inventors:

Hanwoo Cho - Acton MA, US
Richard W. Reeves - Westborough MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 13/36

US Classification:

710311, 710104, 710316, 714 1

Abstract:

A method is provided for utilizing four error correcting code (ECC) pin connections of a PCI/PCI-X bus for one of Grant (GNT) and Request (REQ) pin connections. The method determines a mode of the PCI bus to be PCI-X Mode 1, PCI-X Mode 2, or PCI. If the determined mode is PCI-X Mode 2, the four ECC pin connections are used as ECC pin connections, and if the determined mode is PCI or PCI-X Mode 1, each of the four ECC pin connections is used as a GNT pin connection or a REQ pin connection.

US Patent:

7269681, Sep 11, 2007

Filed:

Dec 1, 2004

Appl. No.:

11/000062

Inventors:

Austen John Hypher - Newton MA, US
Richard W. Reeves - Westboro MA, US
Gerald Robert Talbot - Concord MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 13/36
G06F 1/04

US Classification:

710314, 710306, 710310, 710311, 713600

Abstract:

An integrated device (e. g. , an integrated PCI bridge device) buffers received PCI bus strobe signals and distributes strobe signals for PCI receive data relative to the PCI data lines, enabling all PCI receive data to be latched using locally-generated PCI strobe signals generated based on the same PCI bus strobe signals. In addition, data line latch modules having primary and secondary flip-flops enable the PCI receive data to be held for an entire clock cycle, optimizing conversion between a PCI clock domain and a local clock domain of the PCI bridge device. A transmission circuit also can be configured to transmit data according to either double data rate (DDR) mode or quad data rate (QDR) mode in an efficient manner.

US Patent:

20130315014, Nov 28, 2013

Filed:

May 22, 2012

Appl. No.:

13/477642

Inventors:

Glenn A Dearth - Groton MA, US
Warren R. Anderson - Westborough MA, US
Anwar P. Kashem - Cambridge MA, US
Richard W. Reeves - Westborough MA, US
Edoardo Prete - Arlington MA, US
Gerald E. Talbot - Concord MA, US

International Classification:

G11C 8/18

US Classification:

365193

Abstract:

Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first flip-flop, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.