Richard C Reid

US Patent:

6385672, May 7, 2002

Filed:

Jun 20, 1997

Appl. No.:

08/879406

Inventors:

Richard S. Reid - Mountain View CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 1202

US Classification:

710 56, 710 52, 710130, 711173

Abstract:

The present invention provides a device which facilitates communications between a computer system and a data network by buffering data in transit between the computer system and the data network in a single buffer memory which can be flexibly partitioned into separate transmit and receive buffers. This flexible partitioning allows the relative sizes of the transmit and receive buffers to be optimized across a wide range of buses, data networks and network usage patterns. The transmit and receive buffers are structured as ring buffers within respectively allocated portions of the buffer memory. The buffer memory is controlled by a simple finite state machine controller, which is free from the performance impediments and higher cost associated with a microprocessor-based controller. The present invention also provides support for retransmission of packets that encounter transmission problems such as collisions during transmissions on the data network. The present invention additionally provides the ability to discard incomplete packets.

US Patent:

6956853, Oct 18, 2005

Filed:

Mar 22, 2001

Appl. No.:

09/814619

Inventors:

Glenn William Connery - Sunnyvale CA, US
Gary Jaszewski - Los Gatos CA, US
Richard Reid - Mountain View CA, US

Assignee:

3Com Corporation - Marlborough MA

International Classification:

H04L012/28

US Classification:

370392, 709239

Abstract:

An adapter is provided with intelligence that allows it to separate the header parts of a packet being received from the payload it carries, and in most cases move the payload directly into a destination buffer at the application layer or file system layer. Copies by the intermediate layers of the protocol stack are bypassed, reducing the number of times that the payload of a communication must be copied by the host system. At the network interface, a plurality of packets is received, and the payload of each is bypassed directly into the target destination buffer. The network interface device identifies the packets which are in the sequence of packets carrying payload to be stored in the target buffer by the flow specification carried with such packets. Also, the packets carrying data payload for the file include a sequence number or other identifier by which the network interface is able to determine the offset within the target buffer to which the packet is to be stored.

US Patent:

7899937, Mar 1, 2011

Filed:

Jan 21, 2000

Appl. No.:

09/488942

Inventors:

Richard Hausman - Soquel CA, US
Paul William Sherer - Sunnyvale CA, US
James P. Rivers - Sunnyvale CA, US
Cynthia Zikmund - Boulder Creek CA, US
Glenn W. Connery - Sunnyvale CA, US
Niles E. Strohl - Tracy CA, US
Richard S. Reid - Mountain View CA, US

Assignee:

U.S. Ethernet Innovations, LLC - Tyler TX

International Classification:

G06F 15/16
G06F 3/00
G06F 9/44
G06F 9/46
G06F 13/00

US Classification:

709250, 719321, 719327

Abstract:

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

US Patent:

8239580, Aug 7, 2012

Filed:

Nov 4, 2010

Appl. No.:

12/939604

Inventors:

Richard Hausman - Soquel CA, US
Paul William Sherer - Sunnyvale CA, US
James P. Rivers - Sunnyvale CA, US
Cynthia Zikmund - Boulder Creek CA, US
Glenn W. Connery - Sunnyvale CA, US
Niles E. Strohl - Tracy CA, US
Richard S. Reid - Mountain View CA, US

Assignee:

U.S. Ethernet Innovations, LLC - Tyler TX

International Classification:

G06F 15/16
G06F 3/00
G06F 9/44
G06F 9/46
G06F 13/00

US Classification:

709250, 719321, 719327

Abstract:

In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

US Patent:

61122521, Aug 29, 2000

Filed:

Feb 23, 1998

Appl. No.:

9/028088

Inventors:

Richard Hausman - Soquel CA
Paul William Sherer - Sunnyvale CA
James P. Rivers - Sunnyvale CA
Cynthia Zikmund - Boulder Creek CA
Glenn W. Connery - Sunnyvale CA
Niles E. Strohl - Tracy CA
Richard S. Reid - Mountain View CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 1300
G06F 1332

US Classification:

709250

Abstract:

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

US Patent:

60492589, Apr 11, 2000

Filed:

May 11, 1998

Appl. No.:

9/075373

Inventors:

Marwan A. Fawal - Santa Clara CA
Anthony Liem Pan - Fremont CA
Eric Roger Davis - San Jose CA
Richard Sidney Reid - Mountain View CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

H03H 709

US Classification:

333177

Abstract:

One embodiment of the invention includes a transformer that is at least partially formed on a substrate. The transformer is for electrical isolation and signal filtering. The transformer includes the following elements. A portion of the substrate has two holes through the substrate. A ferrite core is formed in a loop through the two holes. A primary winding is made of a first metal trace. The first metal trace is formed in a spiral around one hole. The first metal trace has at least two primary terminals acting as an input to the transformer. The transformer also includes a secondary winding. The secondary winding is made of a second metal trace. The second metal trace is formed in a spiral around the other hole. The second metal trace has at least two secondary terminals acting as an output from the transformer. The parasitic capacitance of the first metal trace and the magnetizing inductance of the primary winding cause signals received at the primary terminals to be filtered as the signals are passed through the transformer to the secondary terminals.

US Patent:

54855845, Jan 16, 1996

Filed:

Jan 17, 1995

Appl. No.:

8/374491

Inventors:

Richard Hausman - Soquel CA
Paul W. Sherer - Sunnyvale CA
James P. Rivers - Sunnyvale CA
Cynthia Zikmund - Boulder Creek CA
Glenn W. Connery - Sunnyvale CA
Niles E. Strohl - Tracy CA
Richard S. Reid - Mountain View CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 1300
G06F 1332

US Classification:

395842

Abstract:

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

US Patent:

54209870, May 30, 1995

Filed:

Jul 19, 1993

Appl. No.:

8/093380

Inventors:

Richard S. Reid - Mountain View CA
Niles Strohl - Tracy CA
Glenn W. Connery - Sunnyvale CA
Paul W. Sherer - Sunnyvale CA
James P. Rivers - Sunnyvale CA

Assignee:

3 COM Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

395325

Abstract:

In a computer system having a central processing unit which employs software drivers as part of a host for controlling peripheral units and including a bus for connecting with adapters for the peripheral units, wherein each adapter has distributed intelligence means for interpreting simple command information and a nonvolatile storage element for storing default configuration information, including a default port address for communication, a method is provided for configuring such intelligent adapters connected to the bus. The method includes initializing the intelligent adapters by applying power to the bus or by issuing a global reset signal and causing a driver to be loaded by the central processing unit so that the host broadcasts a start key via a sequence of write commands via the bus to any adapters on the bus and to elicit responses from the intelligent adapters in an interactive manner to narrow communication between the intelligent adapters and the host to a single intelligent adapter without first specifying a unique port address. The narrowing process involves causing the intelligent adapters to first rank themselves for communication with the host by referring to unique ordered value information, e. g. , an identification serial number, stored in the nonvolatile storage element, such as an EEPROM element, placed on the adapter.