Richard D Simpson

Address:

17980 SW 57 St, Southwest Ranches, FL 33331

Phone:

9544344952

VIN:

1FMEU63837UA48802

Make:

FORD

Model:

EXPLORER

Year:

2007

US Patent:

6986069, Jan 10, 2006

Filed:

Jul 1, 2002

Appl. No.:

10/188271

Inventors:

Richard R. Oehler - Somers NY, US
Carl Zeitler, Jr. - Austin TX, US
Richard O. Simpson - Austin TX, US

Assignee:

Newisys, Inc. - Austin TX

International Classification:

G06F 1/32
G06F 1/28
G06F 1/26

US Classification:

713320, 713340, 713300

Abstract:

According to the present invention, methods and apparatus are provided for static and dynamic power management of computer systems. A power authority manages power usage levels in computer systems by monitoring power consumption levels and providing power consumption information to the various systems. In one example, the power authority updates power tables to vary aggregate power consumption levels.

US Patent:

7231509, Jun 12, 2007

Filed:

Jan 13, 2005

Appl. No.:

11/034559

Inventors:

Ahmed Gheith - Round Rock TX, US
James Lyle Peterson - Austin TX, US
Richard Ormond Simpson - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/34

US Classification:

712208, 712228

Abstract:

An extended register processor includes a register file having a legacy register set and an extended register set. The extended register set includes a plurality of extended registers accessible only to extended register instructions. The processor maps extended register references to physical extended registers at run time. The processor includes a configurable extended register mapping unit to support this functionality. The mapping unit is accessible to an instruction decoder, which detects extended register references and forwards them to the mapping unit. The mapping unit returns a physical extended register corresponding to the extended register reference in the instruction. The mapping unit is configurable so that, for example, the mapping is specific to a code block. An extended register allocation instruction causes the processor to allocate a portion of the extended register set to the code block in which the declaration is located and to configure the mapping unit to reflect the allocation.

US Patent:

7386796, Jun 10, 2008

Filed:

Apr 1, 2003

Appl. No.:

10/404809

Inventors:

Richard Ormond Simpson - Austin TX, US
David Alan Garrison - Austin TX, US
Yiqin Zhao - Austin TX, US

Assignee:

Newisys Inc. - Austin TX

International Classification:

G06F 3/00

US Classification:

715736

Abstract:

One embodiment of the disclosures made herein is a data processing system adapted for enabling at least one of presence and operating condition of system components installed in the data processing system to be monitored. Examples of presence include installed and uninstalled. Examples of operating conditions include temperature, voltage, current, duty-cycle, etc. The data processing system includes provides a user interface adapted for displaying a 1:1 mapped representation of the data processing system. Operating conditions of installed system components may be assessed via the user interface. A system component that is installed in its respective location in the data processing system (e. g. , in a particular socket) is depicted in the 1:1 mapped representation of the data processing system as being installed in a corresponding location of the data processing system. After performing an operation for installing a particular system component in its respective location of the data processing system (e. g.

US Patent:

52416569, Aug 31, 1993

Filed:

Dec 13, 1991

Appl. No.:

7/807798

Inventors:

Larry K. Loucks - Austin TX
Richard O. Simpson - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1562
G06F 314

US Classification:

395158

Abstract:

In a computer system with a screen display on which is formed a plurality of at least partially overlapping windows associated with different applications, a depth buffer is added to the display adapter for providing with different applications, a depth buffer is added to the display adapter for providing clipping assistance to the software-based window manager. A refresh buffer stores pixel data for each pixel of the display. The window manager monitors the current depth position of each of the pixels within the display and generates a depth value for each pixel. In response to an input request for window rearrangement, the window manager assigns a new depth value to each pixel in a window affected by the request, requests that each application affected by the rearrangement to retransmit pixel values for the pixels associated with at least the portion of a affected window which will become visible as a result of the rearrangement, and transmits new depth values for at least the pixels within the affected portions of such windows. The depth buffer receives and compares the new depth values with the current depth value for each pixel. If the comparator determines that the new pixel value has a depth value associated with the same window or a window closer to the viewer, the depth buffer notifies the refresh buffer to store the new pixel values for each of the applications affected by the rearrangement.

US Patent:

44583117, Jul 3, 1984

Filed:

Oct 9, 1981

Appl. No.:

6/310184

Inventors:

Silous F. Clements - Georgetown TX
Patrick D. Motola - Austin TX
Richard O. Simpson - Austin TX
Shirley F. Swift - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1520
G06F 314

US Classification:

364200

Abstract:

The disclosure relates to an improvement to an information processing system for conducting data processing operations wherein the processing relates to the value of the information and conducting text processing operations wherein the processing affects only the format of information. The improvement provides the combination of means for initiating a data processing session in said system, means for switching to a text processing session before the completion of the data processing session, means for storing the status of the non-completed data processing session during the text processing session, and means for switching back from the text processing session to the non-completed data processing session.

US Patent:

46047107, Aug 5, 1986

Filed:

Mar 12, 1984

Appl. No.:

6/588404

Inventors:

Robert Amezcua - Austin TX
Silous F. Clements - Georgetown TX
John S. Coenen - Austin TX
Ralph H. DaFoe - Austin TX
Michael N. Day - Austin TX
Dennis M. Ross - Austin TX
Richard O. Simpson - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G09G 110
G06F 3023

US Classification:

364900

Abstract:

A method and control apparatus for operating an interactive text processing system wherein the system emulates a terminal for a data processing system which is capable of accessing information from the data processing system data base, copying the information into the text processing system memory, and automatically converting the information from the data processing system format into the text processing system format. Similarly, the text processing system is capable of converting information from its own data base from a text processing system format to a data processing system format and transmitting the information to the data processing system.

US Patent:

46807004, Jul 14, 1987

Filed:

Dec 19, 1986

Appl. No.:

6/845228

Inventors:

Phillip D. Hester - Austin TX
Richard O. Simpson - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300
G06F 936

US Classification:

364200

Abstract:

A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memory wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page Table or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT). The system also has means for hashing a selected virtual address to produce a hashed address. Also included is apparatus for sequentially searching through the linked group of virtual addresses in the combined table until a selected virtual address is located as well as apparatus responsive to the location of a particular selected virtual address for accessing from the first list, the real memory address of the located virtual address.

US Patent:

47945222, Dec 27, 1988

Filed:

Sep 30, 1985

Appl. No.:

6/782323

Inventors:

Richard O. Simpson - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

364200

Abstract:

A method of emulating the instructions of a target computer in the instructions of a host computer to operate the host computer in accordance with the target computer instructions, the target computer having the capability of modifying its own instructions and data during operation, includes the steps of storing the target instructions in a target memory segment, sequentially withdrawing the target instructions from the target memory segment and executing the target instructions in the host computer, constructing a template of the host instructions for each of the target instructions executed, storing each of the templates for reuse each time the corresponding target instruction is to be executed, limiting access to those target instructions in the target memory segment which have been stored in one of the templates to permit only read operations to be performed thereon, and detectng a target instruction which attempts a write operation on one of the target instructions which is in a stored template.