Richard G Vanduren

US Patent:

44518846, May 29, 1984

Filed:

Feb 2, 1982

Appl. No.:

6/345101

Inventors:

Chester A. Heath - Boca Raton FL
Richard G. VanDuren - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 922
G06F 1300
G06F 1506
G06F 1520

US Classification:

364200

Abstract:

A dual mode microprocessor acts either as a front-end IO controller processor relative to a primary host processor and device or as a secondary data processor having independent storage, processing and IO capabilities. Host software prepares a list of device control block (DCB) arrays, which contain primary commands interpretable by the microprocessor so as to evoke these modes. Each DCB contains a chaining bit permitting its interpretation sequence to be chained (or not chained) to another DCB sequence, and a mode bit defining either a high speed DI/DO (HS) mode of operation or a programmable offline (PO) mode. In HS mode the microprocessor conditions associated adapters to transfer a specified amount of data between the host memory and device, performing this transfer in an autonomous manner, i. e. , without assistance from either processor. In PO mode the microprocessor directs associated elements to perform one or more programs of operations defined by secondary commands contained in a command list which is transferred to the microprocessor's memory by special PO mode "LOAD" type DCB's, and interpreted in response to special PO mode type "START" DCB's.

US Patent:

45340110, Aug 6, 1985

Filed:

Feb 2, 1982

Appl. No.:

6/345129

Inventors:

Lawrence P. Andrews - Boca Raton FL
Chester A. Heath - Boca Raton FL
Justin E. Mead - Boca Raton FL
Richard G. VanDuren - Boca Raton FL
Gary A. Janes - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516

US Classification:

364900

Abstract:

This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor.