Rina R Chowdhury

US Patent:

6429531, Aug 6, 2002

Filed:

Apr 18, 2000

Appl. No.:

09/551312

Inventors:

Addi B. Mistry - Austin TX
Rina Chowdhury - Austin TX
Scott K. Pozder - Austin TX
Deborah A. Hagen - Austin TX
Rebecca G. Cole - Austin TX
Kartik Ananthanarayanan - Austin TX
George F. Carney - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2348

US Classification:

257780, 257781, 257784

Abstract:

An interconnect structure, such as a flip-chip structure, including a base pad and a stud formed on the base pad and extending from the base pad is disclosed. The stud and base pad are formed to be continuous and of substantially the same electrically conductive base material. Typically, a solder structure is formed on the stud wherein the solder structure is exposed for subsequent reflow attachment to another structure. The present invention relates to packaging integrated circuits, more particularly to the structure and processing of a stud and bump without the standard under bump metallurgy.

US Patent:

62971557, Oct 2, 2001

Filed:

May 3, 1999

Appl. No.:

9/305093

Inventors:

Cindy Reidsema Simpson - Austin TX
Robert Douglas Mikkola - Austin TX
Matthew T. Herrick - Austin TX
Brett Caroline Baker - Austin TX
David Moralez Pena - Buda TX
Edward Acosta - San Marcos TX
Rina Chowdhury - Austin TX
Marijean Azrak - Austin TX
Cindy Kay Goldberg - Austin TX
Mohammed Rabiul Islam - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H01L 2144

US Classification:

438687

Abstract:

A method for electroplating a copper layer (118) over a wafer (20) powers a cathode of an electroplating system (10) in a manner that obtains improved copper interconnects. A control system (34) powers the cathode of the system (10) with a mix of two or more of: (i) positive low-powered DC cycles (201 or 254); (ii) positive high-powered DC cycles (256 or 310); (iii) low-powered, pulsed, positive-power cycles (306 or 530); (iv) high-powered, pulsed, positive-powered cycles (212, 252, 302, or 352); and/or (v) negative pulsed cycles (214, 304, 510, 528, or 532). The collection of these cycles functions to electroplate copper or a like metal (118) onto the wafer (20). During electroplating, insitu process control and/or endpointing (506, 512, or 520) is performed to further improve the resulting copper interconnect.

US Patent:

6268289, Jul 31, 2001

Filed:

May 18, 1998

Appl. No.:

9/080809

Inventors:

Rina Chowdhury - Austin TX
Ajay Jain - Austin TX
Olubunmi Adetutu - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H01L 2144

US Classification:

438687

Abstract:

A method for forming a copper interconnect begins by depositing a barrier layer (48) within an in-laid region (18). An edge exclusion protection layer (50) is formed over the barrier layer (48), and this layer (50) is processed so that it only lies within the edge exclusion region (20) of the wafer. The layer (50) is removed from active area portions of the wafer so that contact resistance of copper interconnects is not affected. Wet surface processing is used to form a catalyst (64b) on the wafer surface to enable electroless copper plating within active areas of the wafer to form a copper seed layer (52). The layer (52) is not formed in an edge exclusion region (20). Electroplating is then used to thicken the copper material to form a copper layer (54) over the layer (52) wherein the in-laid copper interconnect is completed.