Robert J Baird

US Patent:

6423991, Jul 23, 2002

Filed:

May 1, 2000

Appl. No.:

09/562604

Inventors:

Phillipe Dupuy - Toulouse, FR
Steven L. Merchant - Phoenix AZ
Robert W. Baird - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2710

US Classification:

257207, 257202, 257208

Abstract:

A field effect transistor ( ) has an array of transistors ( ) made up of bonding pads ( ) and sub-arrays of transistors ( ). The bonding pads ( ) are distributed between the sub-arrays of transistors ( ) to reduce the maximum temperature that any portion of the FET ( ) is exposed to while the FET ( ) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion ( ) of an array of transistors ( ).

US Patent:

6593605, Jul 15, 2003

Filed:

Oct 31, 2001

Appl. No.:

10/002705

Inventors:

Young Sir Chung - Chandler AZ
Robert W. Baird - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2710

US Classification:

257207, 257327

Abstract:

A field effect transistor ( ) has an array of transistors ( ) made up of bonding pads ( ) and sub-arrays of transistors ( ). The bonding pads ( ) are distributed between the sub-arrays of transistors ( ) to reduce the maximum temperature that any portion of the FET ( ) is exposed to while the FET ( ) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion ( ) of an array of transistors ( ) or by providing transistors with a higher thermal breakdown in the center of the field effect transistor ( ).

US Patent:

6603157, Aug 5, 2003

Filed:

Nov 2, 2001

Appl. No.:

10/004517

Inventors:

Phillipe Dupuy - Toulouse, FR
Steven L. Merchant - Phoenix AZ
Robert W. Baird - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2710

US Classification:

257202, 257207, 257208

Abstract:

A field effect transistor ( ) has an array of transistors ( ) made up of bonding pads ( ) and sub-arrays of transistors ( ). The bonding pads ( ) are distributed between the sub-arrays of transistors ( ) to reduce the maximum temperature that any portion of the FET ( ) is exposed to while the FET ( ) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion ( ) of an array of transistors ( ).

US Patent:

7220602, May 22, 2007

Filed:

Jul 29, 2005

Appl. No.:

11/192570

Inventors:

Young Sir Chung - Chandler AZ, US
Robert W. Baird - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

438 3, 257414, 257E29167, 3603242, 360E29323

Abstract:

Methods and apparatus are provided for sensing physical parameters. The apparatus comprises a magnetic tunnel junction (MTJ) and a magnetic field source whose magnetic field overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. The MTJ comprises first and second magnetic electrodes separated by a dielectric configured to permit significant tunneling conduction therebetween. The first magnetic electrode has its spin axis pinned and the second magnetic electrode has its spin axis free. The magnetic field source is oriented closer to the second magnetic electrode than the first magnetic electrode. The overall sensor dynamic range is extended by providing multiple electrically coupled sensors receiving the same input but with different individual response curves and desirably but not essentially formed on the same substrate.

US Patent:

7239543, Jul 3, 2007

Filed:

Oct 28, 2005

Appl. No.:

11/262053

Inventors:

Young Sir Chung - Chandler AZ, US
Robert W. Baird - Gilbert AZ, US
Mark A. Durlam - Chandler AZ, US
Gregory W. Grynkewich - Gilbert AZ, US
Eric J. Salter - Scottsdale AZ, US
Jiang-Kai Zuo - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 11/00

US Classification:

365158, 365171, 3651852, 36518909, 365226

Abstract:

An integrated circuit device includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit component. The current sensor may includes a Magnetic Tunnel Junction (“MTJ”) core disposed between the first conductive layer and the second conductive layer. The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.

US Patent:

7256471, Aug 14, 2007

Filed:

Mar 31, 2005

Appl. No.:

11/095302

Inventors:

Won Gi Min - Chandler AZ, US
Robert W. Baird - Gilbert AZ, US
Jiang-Kai Zuo - Chandler AZ, US
Gordon P. Lee - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/00

US Classification:

257530, 257 50, 257E23147, 257410

Abstract:

An antifuse element () having end corners () of a gate electrode () positioned directly above an active area () or bottom electrode. The minimum programming voltage between the gate electrode () and the active area () creates a current path through an insulating layer () positioned therebetween. The high electric field created at the end corners () of the gate electrode () results in a breakdown and rupture of the insulating layer () at points directly beneath the end corners (). This localization of the insulating layer () at the corners () provides for lower post program resistance and variation, and faster programming at a lower programming power. The antifuse elements () when integrated into an array () provide for increased packing density. The array is fabricated to include multiple active areas () for individual antifuse element () programming or a common active area () for multi-element programming.

US Patent:

7264985, Sep 4, 2007

Filed:

Aug 31, 2005

Appl. No.:

11/217146

Inventors:

Young Sir Chung - Chandler AZ, US
Robert W. Baird - Gilbert AZ, US
Mark A. Durlam - Chandler AZ, US
Gregory W. Grynkewich - Gilbert AZ, US
Eric J. Salter - Scottsdale AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

438 48, 438 57, 438 73, 257421, 257295, 365 97, 365173

Abstract:

An integrated circuit device () comprises a substrate () and MRAM architecture () formed on the substrate (). The MRAM architecture () includes a MRAM circuit () formed on the substrate (); and a MRAM cell () coupled to and formed above the MRAM circuit (). Additionally a passive device () is formed in conjunction with the MRAM cell (). The passive device () can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture () and the passive device () facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (), resulting in three-dimensional integration.

US Patent:

7271011, Sep 18, 2007

Filed:

Oct 28, 2005

Appl. No.:

11/262054

Inventors:

Young Sir Chung - Chandler AZ, US
Robert W. Baird - Gilbert AZ, US
Mark A. Durlam - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

438 3, 438238, 438318, 257295, 257E27104

Abstract:

Techniques are provided for sensing a first current produced by an active circuit component. According to these techniques, a current sensor is disposed over the active circuit component. The current sensor includes a Magnetic Tunnel Junction (“MTJ”) core disposed between a first conductive layer and a second conductive layer. The MTJ core can be used to sense the first current and produce a second current based on the first current sensed at the MTJ core.