Robert William Bechdolt

US Patent:

6699765, Mar 2, 2004

Filed:

Aug 29, 2002

Appl. No.:

10/231986

Inventors:

Jay Albert Shideler - Los Altos Hills CA
Jayasimha Swamy Prasad - San Jose CA
Ronald Lloyd Schlupp - Los Gatos CA
Robert William Bechdolt - San Jose CA

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H01L 218222

US Classification:

438312, 438350, 438365, 438481

Abstract:

Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielectric isolation layer overlying the base layer, and an emitter structure overlying the dielectric isolation layer and contacting the base layer through a central aperture in the dielectric layer. The transistor may be a heterojunction bipolar transistor with the base layer formed of a selectively grown silicon germanium alloy. A dielectric spacer may be formed adjacent the emitter structure and over a portion of the base layer.

US Patent:

6913981, Jul 5, 2005

Filed:

May 19, 2003

Appl. No.:

10/441763

Inventors:

Jay Albert Shideler - Los Altos Hills CA, US
Jayasimha Swamy Prasad - San Jose CA, US
Ronald Lloyd Schlupp - Los Gatos CA, US
Robert William Bechdolt - San Jose CA, US

Assignee:

Micrel, Incorporated - San Jose CA

International Classification:

H01L021/8222

US Classification:

438309, 438312, 438365

Abstract:

Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielectric isolation layer overlying the base layer, and an emitter structure overlying the dielectric isolation layer and contacting the base layer through a central aperture in the dielectric layer. The transistor may be a heterojunction bipolar transistor with the base layer formed of a selectively grown silicon germanium alloy. A dielectric spacer may be formed adjacent the emitter structure and over a portion of the base layer.

US Patent:

6933751, Aug 23, 2005

Filed:

Sep 18, 2003

Appl. No.:

10/665645

Inventors:

Thomas S. Wong - San Jose CA, US
Robert W. Bechdolt - San Jose CA, US
Phi Thai - San Jose CA, US

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H03K019/084

US Classification:

326131, 326116, 326118, 257474, 257477

Abstract:

A logic gate is described that has an N-type region, which may be an N-well or N-tub, forming a cathode of one or more Schottky diodes and a collector of an NPN bipolar transistor. Accordingly, the Schottly diodes and transistor do not need to be isolated from one another, resulting in a very compact logic gate. The logic gate forms a portion of a NAND function in one embodiment. One or more Schottky diodes between the collector and base of the bipolar transistor act as a clamp to prevent the transistor from saturating. The clamp diodes can also be used to adjust the output voltage of the gate to ensure downstream transistors can be fully turned off.