Robert C Bedichek

US Patent:

6415379, Jul 2, 2002

Filed:

Oct 13, 1999

Appl. No.:

09/417981

Inventors:

David Keppel - Seattle WA
Robert Cmelik - Sunnyvale CA
Robert Bedichek - Palo Alto CA

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 9455

US Classification:

712209, 712227, 712228, 703 26, 711205, 711202, 711206

Abstract:

A method of maintaining translation context for instructions translated from instructions designed for a target microprocessor to run on a host microprocessor including storing translation context related to each translated host instruction, indicating a translation context for host instructions presently being executed by the host processor, comparing translation context stored for a next host instruction with the translation context for a host instruction presently being executed, executing the next host instruction if the translation context of the next host instruction and the presently executing host instruction compare, and searching for an instruction with translation context which compares to the translation context of the host instruction presently executing if the translation context of the next host instruction and the presently executing host instruction do not compare.

US Patent:

6594821, Jul 15, 2003

Filed:

Mar 30, 2000

Appl. No.:

09/539987

Inventors:

John Banning - Sunnyvale CA
H. Peter Anvin - San Jose CA
Robert Bedichek - Palo Alto CA
Guillermo J. Rozas - Los Gatos CA
Andrew Shaw - Sunnyvale CA
Linus Torvalds - Santa Clara CA
Jason Wilson - San Francisco CA

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 9455

US Classification:

717136, 703 26, 717138, 717139

Abstract:

A method for maintaining consistency between translated host instructions and target instructions from which the host instructions have been translated including the steps of maintaining a copy of a target instruction for which a translated host instruction have been made, comparing the copy of the target instruction with a target instruction at a memory address at which the target instruction from which the copy was made was stored when translated, disabling the translated host instruction if the copy of the target instruction is not the same as the target instruction at the memory address, and executing the translated host instruction if the copy of the target instruction is the same as the target instruction at the memory address.

US Patent:

6845353, Jan 18, 2005

Filed:

Dec 23, 1999

Appl. No.:

09/471447

Inventors:

Robert Bedichek - Palo Alto CA, US
David Keppel - Seattle WA, US
John Banning - Sunnyvale CA, US

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 9455

US Classification:

703 26, 703 23, 703 27, 712209, 714 53, 717138

Abstract:

In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.

US Patent:

6871342, Mar 22, 2005

Filed:

Oct 13, 1999

Appl. No.:

09/417980

Inventors:

Linus Torvalds - Santa Clara CA, US
Robert Bedichek - Palo Alto CA, US
Stephen Johnson - Los Gatos CA, US

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F009/45

US Classification:

717138, 703 26, 703 27, 712228, 712209, 712227

Abstract:

A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

US Patent:

6990658, Jan 24, 2006

Filed:

Oct 13, 1999

Appl. No.:

09/417980

Inventors:

Linus Torvalds - Santa Clara CA, US
Robert Bedichek - Palo Alto CA, US
Stephen Johnson - Los Gatos CA, US

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717138, 703 26, 703 27, 712228, 712209, 712227

Abstract:

A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

US Patent:

7096460, Aug 22, 2006

Filed:

Jun 16, 2003

Appl. No.:

10/463846

Inventors:

John Banning - Sunnyvale CA, US
H. Peter Anvin - San Jose CA, US
Robert Bedichek - Palo Alto CA, US
Guillermo J. Rozas - Los Gatos CA, US
Andrew Shaw - Sunnyvale CA, US
Linus Torvalds - Santa Clara CA, US
Jason Wilson - San Francisco CA, US

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 9/455
G06F 9/318

US Classification:

717136, 712226

Abstract:

In a computer system that translates target instructions from a target instruction set into host instructions from a host instruction set, a method for checking a sequence of target instructions for changes. The method includes testing whether the target instructions at a memory location have changed subsequent to the translating by examining a bit indicator associated with the memory location and determining whether the testing is slowing the operation of the computer system. If the testing is slowing the operation of the computer system, a checking process initiated, which includes storing a copy of the sequence of target instructions and comparing the copy with the sequence of target instructions.

US Patent:

7404181, Jul 22, 2008

Filed:

Aug 21, 2006

Appl. No.:

11/507779

Inventors:

John Banning - Sunnyvale CA, US
H. Peter Anvin - San Jose CA, US
Robert Bedichek - Palo Alto CA, US
Guillermo J. Rozas - Los Gatos CA, US
Andrew Shaw - Sunnyvale CA, US
Linus Torvalds - Santa Clara CA, US
Jason Wilson - San Francisco CA, US

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 9/455

US Classification:

717136, 712226, 717138, 717139

Abstract:

A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.

US Patent:

7617088, Nov 10, 2009

Filed:

Jan 18, 2005

Appl. No.:

11/110085

Inventors:

Robert Bedichek - Palo Alto CA, US
David Keppel - Seattle WA, US
John Banning - Sunnyvale CA, US

International Classification:

G06F 9/455

US Classification:

703 26, 703 23, 703 27, 712209, 717138

Abstract:

In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.