Robert Vernon Berry

US Patent:

6879808, Apr 12, 2005

Filed:

Nov 15, 2000

Appl. No.:

09/713121

Inventors:

William D. Nations - Los Altos CA, US
David S. Puente - Brookville MD, US
Robert E. Berry - Los Altos CA, US

Assignee:

Space Systems/Loral, Inc - Palo Alto CA

International Classification:

H04Q007/20

US Classification:

455 121, 455 301

Abstract:

Broadband data transmission systems and methods that provide point-to-multipoint broadcasting capability to implement Internet access and multimedia distribution services for a very large number of users. An exemplary system comprises a two-way communication link having at least one satellite, at least one user terminal that has two-way communication with the two-way communication link, and at least one gateway that has access to data and has two-way communication with the two-way communication link. The two-way communication link may comprise a low bandwidth two-way communication link, or a low bandwidth request link and high bandwidth data broadcast link. The high bandwidth link preferably broadcasts a wide area coverage beam to allows the requested information to be received by many terminals. The terminal and gateway may each include a cache. Software at the gateway operates to deliver requested data and related data to users using the user's request history and/or user profile.

US Patent:

41971434, Apr 8, 1980

Filed:

Jul 3, 1978

Appl. No.:

5/921637

Inventors:

Robert Berry - Cupertino CA

Assignee:

Fairchild Camera & Instrument Corporation - Mountain View CA

International Classification:

H01L 2980
H01L 21263

US Classification:

148 15

Abstract:

In an oxide isolated semiconductor structure having an epitaxial layer formed on a monocrystalline substrate, a buried, laterally extending PN isolation junction in said structure, and oxidized isolation regions extending through said epitaxial layer to said PN isolation junction, thereby to form a plurality of electrically isolated pockets of semiconductor material, a dopant is located in those regions of the semiconductor material directly adjacent the oxidized isolation regions to prevent unwanted current flow called "channeling. " The region formed by this dopant is often referred to as the field predeposition region. Typically, to form the field predeposition region, a selected dopant is placed in the exposed surface regions of the epitaxial semiconductor material just prior to the formation of the oxidized isolation regions. The field predeposition and oxidation of the epitaxial semiconductor material also cause the formation of a conductive buried region from that portion of the field predeposition dopant in the epitaxial pockets directly adjacent the oxidized semiconductor material. If desired, a collector sink then may be formed in the epitaxial pocket without disrupting the function of the conductive buried region.

US Patent:

41980131, Apr 15, 1980

Filed:

May 19, 1978

Appl. No.:

5/907883

Inventors:

Noah L. Anglin - San Jose CA
Robert H. Berry - San Jose CA

Assignee:

Verbatim Corporation - Sunnyvale CA

International Classification:

G03B 104
G11B 1532
G11B 2304

US Classification:

242192

Abstract:

In a tape cartridge of the type wherein a motor-driven endless belt bears against the supply and take-up rolls of tape to move the tape, and wherein the belt extends about a pair of guide rollers that hold it in tension, the improvement of a drag washer for applying drag to the guide rollers to assure tension in the belt. Each drag washer is bowed, with a central portion having a hole receiving the roller shaft and bearing against an end of the roller, and with a pair of arms bearing against the cartridge frame.

US Patent:

42895740, Sep 15, 1981

Filed:

Jun 9, 1980

Appl. No.:

6/157996

Inventors:

Steven J. Radigan - San Jose CA
Robert L. Berry - San Jose CA

Assignee:

Fairchild Camera & Instrument Corp. - Mountain View CA

International Classification:

H01L 2128
C23F 102

US Classification:

156643

Abstract:

A process for patterning plasma etchable regions on a semiconductor structure includes the steps of forming a layer of an oxide of aluminum over the surface of the semiconductor structure, forming an overlying layer of plasma etchable material on the layer of oxide, and removing undesired portions of the overlying layer by plasma etching to thereby expose portions of the layer of oxide. In some embodiments of the invention the thereby exposed portions of the layer of oxide are then removed, together with any underlying portions of the first layer, by isotropic etching.

US Patent:

44334710, Feb 28, 1984

Filed:

Jan 18, 1982

Appl. No.:

6/340395

Inventors:

Wen-Chuang Ko - San Jose CA
Robert L. Berry - Cupertino CA

Assignee:

Fairchild Camera & Instrument Corporation - Mountain View CA

International Classification:

H01L 2174

US Classification:

29578

Abstract:

A semiconductor structure is fabricated using a process involving all ion implantation and using only five masks prior to metallization. A buried contact mask is used to form a buried contact layer (114), an isolation mask is used to form grooves (130a, 130b) in an epitaxial layer of silicon (113), a self-aligned transistor mask is used to form a mask (134a to 134e) to define the areas in which emitters (138a, 140b, 140c) bases (113, 139) and contact regions (140a) are to be formed, a base exclusion mask (135a,b) is provided to exclude certain impurities from being implanted into a region to be formed of one conductivity type, and a second exclusion mask (137a, 137b) is provided to exclude impurities to be implanted in a region of opposite conductivity type from the prohibited regions of the structure. The last ion implantation of the device is a two-level implantation to yield a shallow implant which provides good ohmic contact to certain to-be-formed metal contact areas and a deep implant to provide current gain control for the base of the NPN transistors (Q. sub. 1, Q. sub. 2). The metal contacts to active regions on the device are formed merely by etching the device to remove a thin oxide (131) over these regions.

US Patent:

41986490, Apr 15, 1980

Filed:

Jul 3, 1978

Appl. No.:

5/921375

Inventors:

Robert Berry - Cupertino CA

Assignee:

Fairchild Camera and Instrument Corporation - Mountain View CA

International Classification:

H01L 2704

US Classification:

357 50

Abstract:

In an oxide isolated semiconductor structure having an epitaxial layer formed on a monocrystalline substrate, a buried, laterally extending PN isolation junction in said structure, and oxidized isolation regions extending through said epitaxial layer to said PN isolation junction, thereby to form a plurality of electrically isolated pockets of semiconductor material, a dopant is located in those regions of the semiconductor material directly adjacent the oxidized isolation regions to prevent unwanted current flow called "channeling. " The region formed by this dopant is often referred to as the field predeposition region. Typically, to form the field predeposition region, a selected dopant is placed in the exposed surface regions of the epitaxial semiconductor material just prior to the formation of the oxidized isolation regions. The field predeposition and oxidation of the epitaxial semiconductor material also cause the formation of a conductive buried region from that portion of the field predeposition dopant in the epitaxial pockets directly adjacent the oxidized semiconductor material. If desired, a collector sink then may be formed in the epitaxial pocket without disrupting the function of the conductive buried region.

US Patent:

45727651, Feb 25, 1986

Filed:

May 2, 1983

Appl. No.:

6/490622

Inventors:

Robert L. Berry - San Mateo CA

Assignee:

Fairchild Camera & Instrument Corporation - Mountain View CA

International Classification:

B44C 122
C03C 1500
C03C 2506

US Classification:

156643

Abstract:

A method of defining narrow regions in an underlying integrated circuit structure includes the steps of depositing a first layer of material 30 having selected etching characteristics on the underlying integrated circuit structure, depositing a second layer of material 32 having etching characteristics different from the first layer 30 on the first layer 30, anisotropically etching the first layer 30 and the second layer 32 from all of the underlying integrated circuit structure 26 except for a desired region having a periphery which includes the narrow region, forming a coating 35 of smoothing material over all of the underlying integrated circuit structure 26 except for the first layer 30, and isotropically etching the first layer 30 to remove it from the surface of the underlying integrated circuit structure 26 to thereby define the narrow region 36. Use of the process to fabricate a compact bipolar transistor structure is also disclosed.

US Patent:

41025164, Jul 25, 1978

Filed:

Apr 14, 1977

Appl. No.:

5/787389

Inventors:

Noah L. Anglin - San Jose CA
Robert H. Berry - San Jose CA

Assignee:

Information Terminals Corporation - Sunnyvale CA

International Classification:

G03B 104
G11B 1532
G11B 2304

US Classification:

242199

Abstract:

In a tape cartridge of the type wherein a motor-driven endless belt bears against the supply and take-up rolls of tape to move the tape, and wherein the belt extends about a pair of guide rollers that hold it in tension, the improvement of a drag washer for applying drag to the guide rollers to assure tension in the belt. Each drag washer is bowed, with a central portion having a hole receiving the roller shaft and bearing against an end of the roller, and with a pair of arms bearing against the cartridge frame.