Robert L Bishop

US Patent:

6373757, Apr 16, 2002

Filed:

Jul 17, 2000

Appl. No.:

09/617155

Inventors:

Robert H. Bishop - Lawrenceville GA

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

G11C 700

US Classification:

365200, 36523003, 36518911, 365240

Abstract:

Preferred memory devices include a first bit line within a first block of memory and a second bit line within a second block of memory. The first bit line is electrically coupled to a reference voltage signal line by a pull-up transistor that turns on in response to an active first bit line pull-up signal (e. g. , /BLPU_IOn=0). The second bit line is also electrically coupled to the reference voltage signal line by a pull-up transistor that turns on in response to an active second bit line pull-up signal (e. g. , /BLPU_IOn+1=0). A control circuit is provided and this control circuit is responsive to a multi-bit shift signal. The control circuit disables generation of the active first bit line pull-up signal in favor of an active second bit line pull-up signal when a value of the shift signal designates replacement of the first block of memory with the second block of memory. The control circuit may also generate signals that disconnect a first IO line associated with a defective first block of memory and substitute a second IO line associated with a functional second block of memory for the first IO line.

US Patent:

6614798, Sep 2, 2003

Filed:

Mar 30, 1999

Appl. No.:

09/281520

Inventors:

Robert H. Bishop - Lawrenceville GA
Bruce C. Grugett - Cumming GA

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

H04L 1254

US Classification:

370428, 3703957

Abstract:

A First-In-First-Out (FIFO) memory device includes a FIFO memory block, a data input interface that writes data into the FIFO memory block in synchronization with a first clock, and a data output interface that reads the data from the FIFO memory block in synchronization with a second clock. The data input interface provides a first indication to the data output interface that the received data has been written into the FIFO memory block. The first indication persists until reset by the data output interface. The data output interface provides a second indication to the data input interface that the received data has been read from the FIFO memory block. The second indication persists until reset by the data input interface.

US Patent:

6930400, Aug 16, 2005

Filed:

Oct 21, 2003

Appl. No.:

10/689946

Inventors:

Robert H. Bishop - Suwanee GA, US
David J. Klein - Duluth GA, US

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

H01L023/48
H01L023/52
H01L029/40

US Classification:

257786, 257773, 257737, 257738, 257780, 257692

Abstract:

A grid array microelectronic package includes a substrate and an array of external connectors on the substrate that are arranged in rows and columns to define a periphery of the array and the interior of the array. A routing channel is provided in the array that increases the periphery of the array by at least four external connectors, compared to absence of the routing channel. The routing channel may be made of two missing external connectors, at least two strapped external connectors and/or at least two “no-connect” external connectors in the array that extend from the periphery of the array towards the interior of the array. Signal conductors may extend along the routing channel.

US Patent:

7796629, Sep 14, 2010

Filed:

Dec 9, 2008

Appl. No.:

12/331372

Inventors:

Angus David Starr MacAdam - Suwanee GA, US
Robert Henry Bishop - Suwanee GA, US
Brian Scott Darnell - Suwanee GA, US

Assignee:

Integrated Device Technology, inc. - San Jose CA

International Classification:

H04L 12/56

US Classification:

370422, 370352

Abstract:

A packet switch including input ports and output ports allocates an output bandwidth of each output port among virtual channels based on bandwidth allocations values corresponding to the virtual channels and a bandwidth precision value of the output port. The bandwidth precision value indicates a number of bandwidth precision bits, which may be outside a bandwidth reservation precision range specified in a serial RapidIO standard. The packet switch receives data packets compliant with the serial RapidIO standard at the input ports, identifies an output port for each data packet, and selects input ports based on the output ports of the data packets. Further, the packet switch routes a data packet from each selected input port to the output port of the data packet, and the output port outputs the data packet by using the output bandwidth of the output port allocated to the virtual channel identified by the data packet.

US Patent:

7974278, Jul 5, 2011

Filed:

Sep 22, 2008

Appl. No.:

12/234877

Inventors:

Angus David Starr MacAdam - Suwanee GA, US
Robert Henry Bishop - Suwanee GA, US
Bruce Lorenz Chin - Decatur GA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

H04L 12/56
H04L 12/50
H04L 12/54

US Classification:

370389, 370401

Abstract:

A communication system includes a packet switch that routes data packets between endpoint devices in the communication system through virtual channels. The packet switch includes output ports each having a link bandwidth for outputting data packets. Each virtual channel is associated with an output port and is allocated a portion of the link bandwidth of the output port. The packet switch receives a data packet identifying a virtual channel at an input port, selects another virtual channel associated with the input port, routes the data packet through the packet switch, and outputs the data packet from the packet switch by using the selected virtual channel. Additionally, the packet switch may select a reliable transmission protocol, a continuous transmission protocol, or a pseudo-continuous transmission protocol for outputting the data packet from the packet switch. In some embodiments, the packet switch modifies the data packet to indicate the selected virtual channel.

US Patent:

8081646, Dec 20, 2011

Filed:

Dec 5, 2008

Appl. No.:

12/328953

Inventors:

Robert Henry Bishop - Suwanee GA, US
Angus David Starr MacAdam - Suwanee GA, US

Assignee:

Integrated Device Technology, inc. - San Jose CA

International Classification:

H04L 12/28

US Classification:

370413, 370422

Abstract:

A packet switch includes virtual output queues for mapping data units of data packets from input ports to output ports of the packet switch. The packet switch selects virtual output queues based on old age indicators of the virtual output queues and routes data units mapped at heads of the selected virtual output queues to output ports of the packet switch. Further, the packet switch may identify a data unit of a multicast data packet mapped at the head of more than one virtual output queue and contemporaneously route the data unit to more than one output port. Additionally, the packet switch may update an old age indicator to indicate a virtual output queue is old if the virtual output queue maps an unserviceable data unit of a multicast data packet and the same data unit is mapped at the head of a selected virtual output queue.

US Patent:

20090073873, Mar 19, 2009

Filed:

Sep 17, 2007

Appl. No.:

11/901419

Inventors:

Angus David MacAdam - Suwanee GA, US
Robert H. Bishop - Suwanee GA, US

International Classification:

G08C 15/00

US Classification:

370219

Abstract:

A data switch () for transferring data includes an A port group (A), a B port group (B), and an AB connector (). The A port group (A) includes an A interface (), a first A port () that is electrically connected to the A interface (), and a second A port () that is electrically connected to the A interface (). The B port group (B) includes a B interface (), a first B port () that is electrically connected to the B interface (), and a second B port () that is electrically connected to the B interface (). The AB connector () directly connects the A interface () to the B interface () so that data from first A port () is transferred from the A interface () to the B interface () via the AB connector (). Additionally, the data switch () includes switching algorithms that control the transfer of data packets between the ports ()-(). The switching algorithms can transfer the data packets in a burst fashion. Further, the switching algorithms can stop the burst fashion in certain circumstances.

US Patent:

20090073968, Mar 19, 2009

Filed:

Sep 17, 2007

Appl. No.:

11/901420

Inventors:

Robert H. Bishop - Suwanee GA, US
Angus David MacAdam - Suwanee GA, US

International Classification:

H04L 12/50

US Classification:

370386

Abstract:

A device () that transfers data includes a destination (), a first data source (), a second data source (), a connector (), and a control system (). The first data source () can have first data to send to the destination (). The second data source () can have second data to send to the destination (). The connector () electrically connects the data sources () to the destination (). The device control system () is electrically connected to the sources () and the destination (). The device control system () utilizes an arbitration progression that sequentially grants access to the connector () to only the data sources () that have data to send to the destination (). The device control system () can evaluate a first data rate of the first data and a second data rate of the second data, and can grant access to the data sources () that have data to send to the destination (). Further, the device control system () can utilize digital hysteresis to control the granting of access to the data sources () that have data to send to the destination (). This can enhance the efficiency of the device () with minimal, if any, increase in size or complexity.