Robert John Bucki

US Patent:

7225422, May 29, 2007

Filed:

Jun 19, 2003

Appl. No.:

10/464879

Inventors:

Robert John Bucki - Cary NC, US
Sang Hoo Dhong - Austin TX, US
Joel Abraham Silberman - Somers NY, US
Osamu Takahashi - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 14, 716 16

Abstract:

A method of designing a logic circuit includes providing a leaf cell having at least one transistor. The leaf is suitable for use as a 1-cell or a 0-cell in the logic circuit. A first array of abutting leaf cells is tiled using at least one 1-cell and at least one 0-cell to define at least one logical expression by the relative positions of the array cells. Length optimized interconnects are added to the array. Each length optimized interconnect terminates at a last leaf cell in the array to which the interconnect makes contact. The leaf cell may be a floating leaf cell in which any pair of abutting cells are electrically isolated from one another until the length optimized interconnects are added to the design. The leaf cell array likely includes a set of rows and a set of columns in which the leaf cells in each row and the set of columns each correspond to an input of the logical expression.

US Patent:

8343814, Jan 1, 2013

Filed:

Aug 17, 2009

Appl. No.:

12/542235

Inventors:

Robert J. Bucki - Cary NC, US
Jagreet S. Atwal - Carrboro NC, US
Joseph S. Barnes - Chapel Hill NC, US
Kerry Bernstein - Underhill VT, US
Eric Robinson - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/335

US Classification:

438142, 438199, 257213, 257E21614

Abstract:

A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.

US Patent:

8513791, Aug 20, 2013

Filed:

May 18, 2007

Appl. No.:

11/750631

Inventors:

Robert J. Bucki - Cary NC, US
Jagreet S. Atwal - Carrboro NC, US
Joseph S. Barnes - Chapel Hill NC, US
Kerry Bernstein - Underhill VT, US
Eric Robinson - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/02

US Classification:

257686, 257 74, 257316, 257690, 257E21614, 365 49, 438109

Abstract:

A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.

US Patent:

8576599, Nov 5, 2013

Filed:

Feb 2, 2012

Appl. No.:

13/364607

Inventors:

Jagreet S. Atwal - Carrboro NC, US
Joseph S. Barnes - Chapel Hill NC, US
Kerry Bernstein - Underhill VT, US
Robert J. Bucki - Cary NC, US
Jason A. Cox - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 15/00
G11C 5/14

US Classification:

365 491, 365 4911, 365 4917, 365226

Abstract:

A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.

US Patent:

20080288720, Nov 20, 2008

Filed:

May 18, 2007

Appl. No.:

11/750676

Inventors:

Jagreet S. Atwal - Carrboro NC, US
Joseph S. Barnes - Chapel Hill NC, US
Kerry Bernstein - Underhill VT, US
Robert J. Bucki - Cary NC, US
Jason A. Cox - Raleigh NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/00
G11C 15/04
H01L 21/8239

US Classification:

711108, 438128, 257E21645, 711E12001

Abstract:

A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.

US Patent:

20080291767, Nov 27, 2008

Filed:

May 21, 2007

Appl. No.:

11/751315

Inventors:

Joseph S. Barnes - Chapel Hill NC, US
Jagreet S. Atwal - Carrboro NC, US
Kerry Bernstein - Underhill VT, US
Robert J. Bucki - Cary NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G11C 8/00
H01L 21/4763

US Classification:

36523005, 438667, 257E21495

Abstract:

A multi-port register file (e.g., memory element) is provided in which each read port of the register file is located in a separate wafer above and/or below the primary data storage element. This is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stacked and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stacked layer.

US Patent:

6535041, Mar 18, 2003

Filed:

Mar 7, 2002

Appl. No.:

10/093440

Inventors:

Robert John Bucki - Cary NC
Sang Hoo Dhong - Austin TX
Jeffrey Herbert Fischer - Cary NC
Joel Abraham Silberman - Somers NY
Osamu Takahashi - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 312

US Classification:

327199, 327200, 365203

Abstract:

A dynamic node keeper device for a dynamic strobe circuit is controlled by the signal at the intermediate node, that is, the signal at the output of the strobe component. By controlling the dynamic node keeper device through the strobe component output, the keeper device is active or conductive only when necessary to protect against noises in the pull down network for the strobe circuit. At all other times in the course of operation of the dynamic strobe circuit, the dynamic node keeper device according to the invention is nonconductive or inactive. Thus, the dynamic strobe circuit according to the invention reduces power consumption.

US Patent:

20170338215, Nov 23, 2017

Filed:

May 20, 2016

Appl. No.:

15/160992

Inventors:

- San Diego CA, US
Giridhar Nallapati - San Diego CA, US
Da Yang - San Diego CA, US
Kern Rim - San Diego CA, US
Robert Bucki - Raleigh NC, US
Choh Fei Yeap - Hsinchu City, TW

International Classification:

H01L 27/02
H01L 27/092
H01L 27/118

Abstract:

A heterogeneous cell array includes a first column of cells and a second column of cells. The first column of cells includes a first cell having a first area and a second cell having the first area. The first cell includes two fin-type field effect transistors having a first number of fins and the second cell includes two fin-type field effect transistors having the first number of fins. The second column of cells includes a third cell having a second area. The third cell is adjacent to the first cell and to the second cell, and the third cell includes two fin-type field effect transistors having a second number of fins. The second area is greater than the first area, and the second number of fins is greater than the first number of fins.