Robert Charles Burd

US Patent:

6380724, Apr 30, 2002

Filed:

Nov 16, 1999

Appl. No.:

09/442208

Inventors:

Eric W. Mahurin - Austin TX
Robert C. Burd - San Jose CA
Jeffrey A. Correll - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G01R 3102

US Classification:

324 731, 324 7659, 324 7661, 714726, 714729

Abstract:

A method and circuitry for an undisturbed scannable state element. A scannable state element, implemented in a scan chain for testing an integrated circuit, includes both a dual-ported flop circuit and a shadow flop circuit. The dual-ported flop circuit includes both a master cell and a slave cell, while the shadow flop includes only a master cell, and utilizes the slave cell of the dual-ported flop. During scan shifting, scan data is shifted through the shadow flop and the slave cell of the dual-ported flop, bypassing the master cell. Since the data output of the dual-ported flop originates in the master cell, the state of the data in the dual-ported flop is not disturbed by the scan. Scan data may also be latched into the master cell from the scan chain or from the master cell into the scan chain through a scan data output in the slave cell. A shadow control logic circuit routes scan clock signals to either the dual-ported flop or the shadow flop, depending on whether scan shifting operations are taking place. Each shadow control logic circuit may be coupled to a plurality of shadow flops and dual-ported flops, thereby controlling a plurality of scannable state elements.

US Patent:

57740054, Jun 30, 1998

Filed:

Aug 30, 1996

Appl. No.:

8/706340

Inventors:

Hamid Partovi - Sunnyvale CA
Robert C. Burd - Santa Clara CA
Udin Salim - San Jose CA
Frederick Weber - San Jose CA
Luigi DiGregorio - Sunnyvale CA
Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 3356

US Classification:

327210

Abstract:

A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially setup and clock-to-output times. The flip-flop consumes no static power.

US Patent:

59907177, Nov 23, 1999

Filed:

Mar 9, 1998

Appl. No.:

9/037198

Inventors:

Hamid Partovi - Sunnyvale CA
Robert C. Burd - Santa Clara CA
Udin Salim - San Jose CA
Frederick Weber - San Jose CA
Luigi Di Gregorio - Sunnyvale CA
Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 3356

US Classification:

327210

Abstract:

A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

US Patent:

RE357979, May 19, 1998

Filed:

Apr 19, 1995

Appl. No.:

8/425753

Inventors:

Andrew C. Graham - Austin TX
Michael G. France - Portland OR
Robert C. Burd - Santa Clara CA
Mark E. Fitzpatrick - San Jose CA

Assignee:

TriQuint Semiconductor, Inc. - Hillsboro OR

International Classification:

H03K 738

US Classification:

326 40

Abstract:

A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.

US Patent:

50049712, Apr 2, 1991

Filed:

Apr 5, 1990

Appl. No.:

7/505858

Inventors:

Mark E. Fitzpatrick - San Jose CA
Robert C. Burd - Sunnyvale CA

Assignee:

Gazelle Microcircuits, Inc. - Santa Clara CA

International Classification:

G05F 146
G05F 308

US Classification:

323312

Abstract:

A switch means is disclosed which enables two or more terminals normally having a wide operating voltage to be connected by a pass transistor. A biasing means applies a voltage to the gate of the pass transistor which turns on the pass transistor without forward biasing any inherent diodes within the pass transistor.

US Patent:

6087872, Jul 11, 2000

Filed:

Feb 23, 1998

Appl. No.:

9/028960

Inventors:

Hamid Partovi - Sunnyvale CA
Robert C. Burd - Santa Clara CA
Udin Salim - San Jose CA
Frederick Weber - San Jose CA
Luigi Di Gregorio - Sunnyvale CA
Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 312

US Classification:

327201

Abstract:

A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

US Patent:

52124584, May 18, 1993

Filed:

Sep 23, 1991

Appl. No.:

7/764020

Inventors:

Mark E. Fitzpatrick - San Jose CA
Robert C. Burd - San Jose CA

Assignee:

TriQuint Semiconductor, Inc. - Santa Clara CA

International Classification:

H03F 345

US Classification:

330288

Abstract:

A current mirror compensation circuit is disclosed herein which automatically adjusts the operating conditions of a current mirror so as to compensate for the voltage dependent current characteristics of a current load which a current mirror output is intended to match. In one embodiment, this compensation circuit compares a voltage level at the output of a current source with a voltage level at a corresponding node in the current programming portion of a current mirror. If a difference in these voltages is detected, the compensation circuit adjusts the current flow through the current programming portion of the current mirror to be equal to the output current through the current source. Therefore, since the current mirror output portion mirrors the current through the programming position, the currents through the output portion will match the current through the current source.

US Patent:

52045552, Apr 20, 1993

Filed:

Apr 2, 1992

Appl. No.:

7/863327

Inventors:

Andrew C. Graham - Sunnyvale CA
Michael G. France - Fremont CA
Robert C. Burd - Sunnyvale CA
Mark E. Fitzpatrick - San Jose CA

Assignee:

Gazelle Microcircuits, Inc. - Santa Clara CA

International Classification:

H03K 513
H03K 1902

US Classification:

307465

Abstract:

A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.