Robert L Burd

US Patent:

57740054, Jun 30, 1998

Filed:

Aug 30, 1996

Appl. No.:

8/706340

Inventors:

Hamid Partovi - Sunnyvale CA
Robert C. Burd - Santa Clara CA
Udin Salim - San Jose CA
Frederick Weber - San Jose CA
Luigi DiGregorio - Sunnyvale CA
Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 3356

US Classification:

327210

Abstract:

A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially setup and clock-to-output times. The flip-flop consumes no static power.

US Patent:

59907177, Nov 23, 1999

Filed:

Mar 9, 1998

Appl. No.:

9/037198

Inventors:

Hamid Partovi - Sunnyvale CA
Robert C. Burd - Santa Clara CA
Udin Salim - San Jose CA
Frederick Weber - San Jose CA
Luigi Di Gregorio - Sunnyvale CA
Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 3356

US Classification:

327210

Abstract:

A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

US Patent:

6087872, Jul 11, 2000

Filed:

Feb 23, 1998

Appl. No.:

9/028960

Inventors:

Hamid Partovi - Sunnyvale CA
Robert C. Burd - Santa Clara CA
Udin Salim - San Jose CA
Frederick Weber - San Jose CA
Luigi Di Gregorio - Sunnyvale CA
Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 312

US Classification:

327201

Abstract:

A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

US Patent:

52045552, Apr 20, 1993

Filed:

Apr 2, 1992

Appl. No.:

7/863327

Inventors:

Andrew C. Graham - Sunnyvale CA
Michael G. France - Fremont CA
Robert C. Burd - Sunnyvale CA
Mark E. Fitzpatrick - San Jose CA

Assignee:

Gazelle Microcircuits, Inc. - Santa Clara CA

International Classification:

H03K 513
H03K 1902

US Classification:

307465

Abstract:

A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.

US Patent:

52085554, May 4, 1993

Filed:

Sep 23, 1991

Appl. No.:

7/764039

Inventors:

Andrew C. Graham - Sunnyvale CA
Robert C. Burd - San Jose CA

Assignee:

TriQuint Semiconductor, Inc. - Santa Clara CA

International Classification:

H03L 7085

US Classification:

331 1A

Abstract:

A circuit is which, when used in a voltage controlled oscillator (VCO) circuit, detects a frequency on the output of the VCO and, if this output frequency is above a certain value, the circuit forces the output frequency of the VCO to decrease until it is below the certain value. This acts to keep the output frequency of the VCO below a selected frequency which can be accurately processed by the feedback circuits driven by the VCO. Once the output frequency of the VCO is below the certain value, the circuit stops forcing the output frequency to decrease, and the circuit becomes transparent. At this point, the conventional feedback circuitry driving the VCO takes over the adjustment of the VCO output frequency.

US Patent:

57640890, Jun 9, 1998

Filed:

Aug 30, 1996

Appl. No.:

8/706212

Inventors:

Hamid Partovi - Sunnyvale CA
Robert C. Burd - Santa Clara CA
Udin Salim - San Jose CA
Frederick Weber - San Jose CA
Luigi Di Gregorio - Sunnyvale CA
Donald A. Draper - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 3037

US Classification:

327200

Abstract:

A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.