Robert K Busse

US Patent:

51322358, Jul 21, 1992

Filed:

Mar 29, 1991

Appl. No.:

7/678578

Inventors:

Richard K. Williams - Cupertino CA
Robert W. Busse - Mountain View CA
Richard A. Blanchard - Los Altos CA

Assignee:

Siliconix Incorporated - Santa Clara CA

International Classification:

H01L 21265

US Classification:

437 31

Abstract:

A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer. Using this method, the high concentration of slow diffusing N type antimony or arsenic dopant in the buried layer will not out-diffuse into the N-well region and adversely affect the breakdown voltage between the source or drain and the N-well. The out-diffusing of the phosphorus into the epitaxial layer, however, will merge with the phosphorus diffusion from the top to form a uniform N type concentration in the N-well.

US Patent:

52182282, Jun 8, 1993

Filed:

Mar 11, 1992

Appl. No.:

7/849723

Inventors:

Richard K. Williams - Cupertino CA
Robert W. Busse - Mountain View CA
Richard A. Blanchard - Los Altos CA

Assignee:

Siliconix Inc. - Santa Clara CA

International Classification:

H01L 2702
H01L 2972

US Classification:

257593

Abstract:

A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer. Using this method, the high concentration of slow diffusing N type antimony or arsenic dopant in the buried layer will not out-diffuse into the N-well region and adversely affect the breakdown voltage between the source or drain and the N-well. The out-diffusing of the phosphorus into the epitaxial layer, however, will merge with the phosphorus diffusion from the top to form a uniform N type concentration in the N-well.

US Patent:

52586367, Nov 2, 1993

Filed:

Dec 12, 1991

Appl. No.:

7/808024

Inventors:

Vladimir Rumennik - Los Altos CA
Robert W. Busse - Mountain View CA

Assignee:

Power Integrations, Inc. - Mountain View CA

International Classification:

H01L 2980
H01L 29520
H01L 29784

US Classification:

257339

Abstract:

A field effect transistor (FET), according to the present invention, comprises a source and drain pair of electrodes having non-uniform charge distributions between them, such as results from small radius tips, and has a gate and channel structure that exists only between points of the source and drain pair that have the less intense charge distributions, e. g. , areas not involving any small radius tips. The gate and channel structure is such that, given the non-uniform charge distributions between the source and drain pair of electrodes, the electric field is reduced around the tip by eliminating the n-well junction near the source-drain fingertips.