Robert J Carr

US Patent:

6777291, Aug 17, 2004

Filed:

Apr 30, 2003

Appl. No.:

10/427559

Inventors:

Paul J. Rudeck - Boise ID
Graham Wolstenholme - Boise ID
Robert Carr - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21336

US Classification:

438257, 438258, 438259, 438593, 438594

Abstract:

The invention includes a method of making a programmable memory device. At least one floating gate layer is formed over a semiconductor substrate. A dielectric material is formed over the at least one floating gate layer, and a mass consisting essentially of W is formed over the dielectric material. The mass has a pair of opposing sidewalls. A first layer is formed over the mass and along the sidewalls of the mass, and a second layer is formed over the first layer. The second layer extends over the mass and along the sidewalls of the mass, and has a different composition than the first layer. After the second layer is formed, the first and second layers are anisotropically etched to form sidewall spacers extending along the sidewalls of the mass.

US Patent:

6803624, Oct 12, 2004

Filed:

Jul 3, 2002

Appl. No.:

10/190422

Inventors:

Paul J. Rudeck - Boise ID
Graham Wolstenholme - Boise ID
Robert Carr - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 29788

US Classification:

257315, 257314

Abstract:

The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tungsten, and a second mass consisting essentially of one or more nitride compounds. The invention includes a memory device having a floating gate and a dielectric material over the floating gate. The device has a mass consisting essentially of tungsten over the dielectric material, with the mass having a pair of opposing sidewalls. A pair of sidewall spacers are along the opposing sidewalls of the mass. The sidewall spacers comprise a first layer consisting essentially of one or more nitride compounds and a second layer different from the first layer. The invention includes methods of making memory devices.

US Patent:

6873005, Mar 29, 2005

Filed:

May 4, 2004

Appl. No.:

10/839331

Inventors:

Paul J. Rudeck - Boise ID, US
Graham Wolstenholme - Boise ID, US
Robert Carr - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L029/788

US Classification:

257315, 257314

Abstract:

The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tungsten, and a second mass consisting essentially of one or more nitride compounds. The invention includes a memory device having a floating gate and a dielectric material over the floating gate. The device has a mass consisting essentially of tungsten over the dielectric material, with the mass having a pair of opposing sidewalls. A pair of sidewall spacers are along the opposing sidewalls of the mass. The sidewall spacers comprise a first layer consisting essentially of one or more nitride compounds and a second layer different from the first layer. The invention includes methods of making memory devices.

US Patent:

7091549, Aug 15, 2006

Filed:

Dec 9, 2004

Appl. No.:

11/007885

Inventors:

Paul J. Rudeck - Boise ID, US
Graham Wolstenholme - Boise ID, US
Robert Carr - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 29/788

US Classification:

257315, 257314, 257E21626, 257E2164

Abstract:

The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tungsten, and a second mass consisting essentially of one or more nitride compounds. The invention includes a memory device having a floating gate and a dielectric material over the floating gate. The device has a mass consisting essentially of tungsten over the dielectric material, with the mass having a pair of opposing sidewalls. A pair of sidewall spacers are along the opposing sidewalls of the mass. The sidewall spacers comprise a first layer consisting essentially of one or more nitride compounds and a second layer different from the first layer. The invention includes methods of making memory devices.

US Patent:

8288083, Oct 16, 2012

Filed:

Nov 5, 2010

Appl. No.:

12/940802

Inventors:

Zishu Zhang - Boise ID, US
Anton deVilliers - Boise ID, US
Robert Carr - Boise ID, US
Farrell Good - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G03F 7/26

US Classification:

430325, 430322, 430323, 430324

Abstract:

Some embodiments include methods in which spaced-apart first features are formed from a first material having a reflow temperature. Second material is formed along sidewalls of the first features, and third material is formed over the second material and the first features. The third material may be formed at a temperature above the reflow temperature of the first material, and the second material may support the first features so that the first features do not collapse even though they are exposed to such temperature. In some embodiments the third material has an undulating topography. Fourth material may be formed within the valleys of the undulating topography, and subsequently the first features may be removed together with at least some of the third material to leave a pattern comprising second features formed from the second material and pedestals formed from the fourth material.

US Patent:

8476002, Jul 2, 2013

Filed:

Sep 10, 2012

Appl. No.:

13/609027

Inventors:

Zishu Zhang - Boise ID, US
Anton J. deVilliers - Boise ID, US
Robert Carr - Boise ID, US
Farrell Good - Meridian IA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G03F 7/26

US Classification:

430325, 430322, 430323, 430324

Abstract:

Some embodiments include methods in which spaced-apart first features are formed from a first material having a reflow temperature. Second material is formed along sidewalls of the first features, and third material is formed over the second material and the first features. The third material may be formed at a temperature above the reflow temperature of the first material, and the second material may support the first features so that the first features do not collapse even though they are exposed to such temperature. In some embodiments the third material has an undulating topography. Fourth material may be formed within the valleys of the undulating topography, and subsequently the first features may be removed together with at least some of the third material to leave a pattern comprising second features formed from the second material and pedestals formed from the fourth material.

US Patent:

20050287793, Dec 29, 2005

Filed:

Jun 29, 2004

Appl. No.:

10/881303

Inventors:

Aaron Blanchet - Boise ID, US
Roger Lindsay - Boise ID, US
Robert Carr - Boise ID, US

International Classification:

H01L021/336
H01L029/40

US Classification:

438629000, 257774000, 257773000, 257775000, 257776000, 438638000, 438619000

Abstract:

Methods and apparatus are described to facilitate forming of polysilicon contact plugs with an improved diffusion barrier that can be formed in conjunction with other process steps. Embodiments of the present invention are formed by recessing the polysilicon plug below the surface of the insulation layer, allowing the depression formed at the interface of the insulating layer and the top of the polysilicon plug to be filled with a diffusion barrier/liner layer before deposition and etching of the metal interconnection layer. This allows the etching of the polysilicon contact plug and deposition of the barrier layer to occur along with other process steps. In an embodiment of the present invention the peripheral metal contact plugs and polysilicon contact plugs of a memory array are deposited with liner material and removed in a series of concurrent process steps.

US Patent:

20060033215, Feb 16, 2006

Filed:

Oct 17, 2005

Appl. No.:

11/252130

Inventors:

Aaron Blanchet - Boise ID, US
Roger Lindsay - Boise ID, US
Robert Carr - Boise ID, US

International Classification:

H01L 23/48

US Classification:

257774000

Abstract:

Methods and apparatus are described to facilitate forming of polysilicon contact plugs with an improved diffusion barrier that can be formed in conjunction with other process steps. Embodiments of the present invention are formed by recessing the polysilicon plug below the surface of the insulation layer, allowing the depression formed at the interface of the insulating layer and the top of the polysilicon plug to be filled with a diffusion barrier/liner layer before deposition and etching of the metal interconnection layer. This allows the etching of the polysilicon contact plug and deposition of the barrier layer to occur along with other process steps. In an embodiment of the present invention the peripheral metal contact plugs and polysilicon contact plugs of a memory array are deposited with liner material and removed in a series of concurrent process steps.