Robert Cavin

US Patent:

7143320, Nov 28, 2006

Filed:

Dec 31, 2001

Appl. No.:

10/039649

Inventors:

Robert D. Cavin - Palo Alto CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714704, 370333, 370311, 370252, 455505, 455506, 455 631, 455 78, 455 6713, 375346

Abstract:

A method for increasing data throughput on a wireless local area network in the presence of intermittent interference. The method of one embodiment comprises receiving a data packet through a wireless channel. Quality of the wireless channel is evaluated. A packet error ratio (PER) value is calculated for the data packet. The PER value is checked as to whether it is within an acceptable level. A determination is made as to whether an intermittent noise is affecting the PER value.

US Patent:

7224830, May 29, 2007

Filed:

Feb 4, 2003

Appl. No.:

10/358761

Inventors:

Ara V. Nefian - Fremont CA, US
Robert D. Cavin - Palo Alto CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06K 9/00
H04N 13/00

US Classification:

382154, 382285, 715863, 348 42

Abstract:

Human gestures are detected and/or tracked from a pair of digital video images. The pair of images may be used to provide a set of observation vectors that provide a three dimensional position of a subject's upper body. The likelihood of each observation vector representing an upper body component may be determined. Initialization of the model for detecting and tracking gestures may include a set of assumptions regarding the initial position of the subject in a set of foreground observation vectors.

US Patent:

7984273, Jul 19, 2011

Filed:

Dec 31, 2007

Appl. No.:

11/967482

Inventors:

Eric Sprangle - Austin TX, US
Anwar Rohillah - Austin TX, US
Robert Cavin - San Francisco CA, US
Tom Forsyth - Kirkland WA, US
Michael Abrash - Kirkland WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/312

US Classification:

712225, 712 4, 712 6

Abstract:

A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.

US Patent:

8065488, Nov 22, 2011

Filed:

Oct 20, 2010

Appl. No.:

12/908183

Inventors:

Eric Sprangle - Austin TX, US
Anwar Rohillah - Austin TX, US
Robert Cavin - San Francisco CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/12

US Classification:

711134, 711136, 711E1207, 711E12071

Abstract:

A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data.

US Patent:

8108614, Jan 31, 2012

Filed:

Dec 31, 2007

Appl. No.:

11/967413

Inventors:

Eric Sprangle - Austin TX, US
Anwar Rohillah - Austin TX, US
Robert Cavin - Palo Alto CA, US

International Classification:

G06F 12/12

US Classification:

711134, 711136, 711E1207, 711E12071

Abstract:

A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data.

US Patent:

20080243985, Oct 2, 2008

Filed:

Mar 30, 2007

Appl. No.:

11/731580

Inventors:

Ping Tak Peter Tang - Castro Valley CA, US
Robert Cavin - San Francisco CA, US

International Classification:

G06F 7/38

US Classification:

708502

Abstract:

A new function for calculating the reciprocal residual of a floating-point number X is defined as recip_residual(X)=1−X*recip(X), where recip(X) represents the reciprocal of X. The function may be implemented using a fused multiply-add unit in a processor. The reciprocal value of X, recip(X), may be obtained from a lookup table. The recip_residual function may help reduce the latency of many multiplicative functions that are based on products of multiple numbers and can be expressed in simple terms of functions on each individual number (e.g., log(U*V)=log(U)+log(V)).

US Patent:

20090171994, Jul 2, 2009

Filed:

Dec 31, 2007

Appl. No.:

11/967492

Inventors:

Eric Sprangle - Austin TX, US
Anwar Rohillah - Austin TX, US
Robert Cavin - San Francisco CA, US
Tom Forsyth - Kirkland WA, US
Michael Abrash - West Kirkland WA, US

International Classification:

G06F 17/30

US Classification:

707101, 707E17009

Abstract:

A system and method for generating a single compressed vector including two or more predetermined attribute values. For each of a plurality of data points such as pixels, if a first and a second attribute values of the data point are equal to a first and a second, respectively, of the two or more predetermined attribute values, the compressed vector is used to operate on the data point. Other embodiments are described and claimed.

US Patent:

20090172349, Jul 2, 2009

Filed:

Dec 26, 2007

Appl. No.:

11/964631

Inventors:

Eric Sprangle - Austin TX, US
Robert D. Cavin - Sunnyvale CA, US
Anwar Rohillah - Austin TX, US
Douglas M. Carmean - Beaverton OR, US

International Classification:

G06F 9/30

US Classification:

712 4, 712E09021

Abstract:

A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.