Robert Lance Colwell

age ~47

from Roscoe, IL

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Also known as:

Robert L Colwell
Robert D Colwell
Rob L Colwell
Robert Cowell
Bob Colwell
Richard Colwell
Robert Robert
Robert Calwell

Connected to:

Robert Colwell Phones & Addresses

Roscoe, IL
South Beloit, IL
Rockton, IL
Byron, IL
Shelton, CT

Resumes

Robert Colwell

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Robert Colwell

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Robert Colwell

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Robert Colwell

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Lawyers & Attorneys

Robert Colwell - Lawyer

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Specialties:

Real Estate Law

ISLN:

901535083

Admitted:

1991

University:

Arizona State University, B.S., 1985

Law School:

Pepperdine University, J.D., 1990

Robert Colwell - Lawyer

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Office:

Kilpatrick Townsend & Stockton LLP

Specialties:

Patent Prosecution & Counseling
International Strategy
Licensing
Transactional Intellectual Property

ISLN:

908259012

Admitted:

1973

University:

University of Kansas, B.S., 1969; University of Kansas, B.S., 1969; University of Kansas, B.S., 1969; University of Kansas, M.S., 1970; University of Kansas, M.S., 1970; University of Kansas, M.S., 1970

Law School:

Stanford University, J.D., 1973

License Records

Robert D. Colwell

License #:

8067 - Active

Issued Date:

Aug 30, 1983

Renew Date:

Dec 1, 2015

Expiration Date:

Nov 30, 2017

Type:

Certified Public Accountant

Robert D. Colwell

License #:

8067 - Active

Issued Date:

Aug 30, 1983

Renew Date:

Dec 1, 2015

Expiration Date:

Nov 30, 2017

Type:

Certified Public Accountant

Robert D. Colwell

License #:

8067 - Active

Issued Date:

Aug 30, 1983

Renew Date:

Dec 1, 2015

Expiration Date:

Nov 30, 2017

Type:

Certified Public Accountant

Isbn (Books And Publications)

The Pentium Chronicles: The People, Passion, And Politics Behind Intel's Landmark Chips

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Author
Robert P. Colwell

ISBN #
0471736171

Biota: The Biodiversity Database Manager

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Author
Robert K. Colwell

ISBN #
0878931287

Systematics and Host Plant Affiliations of Hummingbird Flower Mites of the Genera Tropicoseius Baker & Yunker and Rhinoiseius Baker & Yunker: Acari Mesostigmata Ascidae

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Author
Robert K. Colwell

ISBN #
0938522671

Manual of Remote Sensing

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Author
Robert N. Colwell

ISBN #
0686231082

Manual of Remote Sensing

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Author
Robert N. Colwell

ISBN #
0937294411

Guide to Bicycle Trails

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Author
Robert Colwell

ISBN #
0811707687

Introduction to Backpacking

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Author
Robert Colwell

ISBN #
0811709094

Introduction to Foot Trails in America

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Author
Robert Colwell

ISBN #
0811709140

Us Patents

Instruction Storage And Cache Miss Recovery In A High Speed Multiprocessing Parallel Processing Apparatus
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US Patent:

51796805, Jan 12, 1993
Filed:

May 30, 1991
Appl. No.:

7/707917
Inventors:

Robert P. Colwell - Guilford CT
John O'Donnell - Guilford CT
David B. Papworth - Guilford CT
Paul K. Rodman - Madison CT
Assignee:

Digital Equipment Corporation - Maynard MA
International Classification:

G06F 1208
US Classification:

395425
Abstract:

A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

Hierarchical Priority Branch Handling For Parallel Execution In A Parallel Processor
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US Patent:

48335991, May 23, 1989
Filed:

Apr 20, 1987
Appl. No.:

7/041081
Inventors:

Robert P. Colwell - Guilford CT
John O'Donnell - Guilford CT
David B. Papworth - Guilford CT
Paul K. Rodman - Madison CT
Assignee:

Multiflow Computer, Inc. - Branford CT
International Classification:

G06F 928
G06F 942
US Classification:

364200
Abstract:

In a parallel data processing system having a plurality of separately operating arithmetic processing units, a method and apparatus allows a plurality of branch instructions to be operated upon in a single machine cycle. The branch instructions have associated therewith a hierarchical priority system and the method and apparatus determine which branch, if any, should be taken. In particular, the method and apparatus simultaneously determine, during the parallel execution of the branch instructions, whether any branch test condition associated with a branch instruction is true, and independently, the target address for each branch instruction and a fall-through instruction address if a branch instruction is not taken.

Virtual Address Table Look Aside Buffer Miss Recovery Method And Apparatus
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US Patent:

49204777, Apr 24, 1990
Filed:

Apr 20, 1987
Appl. No.:

7/040990
Inventors:

Robert P. Colwell - Guilford CT
John O'Donnell - Guilford CT
David B. Papworth - Guilford CT
Paul K. Rodman - Madison CT
Assignee:

Multiflow Computer, Inc. - Branford CT
International Classification:

G06F 1208
G06F 938
G06F 1100
US Classification:

364200
Abstract:

A data processor has a central processing unit and at least one pipelined memory controller circuitry. The central processing unit addresses data in the memory using a virtual address memory table lookaside buffer and features a data miss recovery circuitry wherein, after a memory access error condition has been detected, the instruction causing the error condition, and those instructions entering the memory pipeline after the instruction causing the error condition, are replayed. The method and apparatus for replaying the instructions use first in-first out buffers for storing the virtual address data and instruction status data relating to each memory access instruction. That stored data is then retrieved after an error condition is detected so that the instruction sequence, beginning at the data miss, can be replayed.

Instruction Storage Method With A Compressed Format Using A Mask Word
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US Patent:

50578375, Oct 15, 1991
Filed:

Jan 30, 1990
Appl. No.:

7/476108
Inventors:

Robert P. Colwell - Guilford CT
John O'Donnell - Guilford CT
David B. Papworth - Guilford CT
Paul K. Rodman - Madison CT
Assignee:

Digital Equipment Corporation - Maynard MA
International Classification:

H03M 500
US Classification:

341 55
Abstract:

A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

High Bandwidth Multiple Computer Bus Apparatus
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US Patent:

53075064, Apr 26, 1994
Filed:

Sep 16, 1992
Appl. No.:

7/945571
Inventors:

Robert P. Colwell - Guilford CT
John O'Donnell - Guilford CT
David B. Papworth - Guilford CT
Paul K. Rodman - Madison CT
Assignee:

Digital Equipment Corporation - Maynard MA
International Classification:

G06F 1340
US Classification:

395800
Abstract:

A parallel processor has a plurality of communication buses advantageously interconnecting the arithmetic processor elements, the memory controller elements, a global controller circuitry, and input/output processors. The processor preferably has at least one central processing unit cluster, the cluster having at least one integer processor and one floating point processor. A plurality of I/F buses interconnect the integer and floating point processors of a cluster for communications therebetween. Integer load buses connect the integer processors of each cluster and selectively connect those processors to the memory controllers for transferring data from memory to the clusters and for providing inter-integer processor data communications. A plurality of floating point load buses connect the floating point processors of the clusters to selected memory controllers for transferring data from the controllers to the floating point processors and for providing inter-floating point processor data communications. A plurality of physical address buses provide one-way communications for transferring memory addresses from the integer processors to the memories and a plurality of storage buses connect the floating point processors to the memory controllers along a one-way communications path for transferring data to be stored in the memories.

Amazon

The poems of William Morris: selected and ed. by Percy Robert Colwell.

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Originally published in 1905. This volume from the Cornell University Library's print collections was scanned on an APT BookScan and converted to JPG 2000 format by Kirtas Technologies. All titles scanned cover to cover and pages may include marks, notations and other marginalia present in the orig...

Author
William Morris

Binding
Paperback

Pages
406

Publisher
Cornell University Library

ISBN #
1429786221

EAN Code
9781429786225

ISBN #
2

The Pentium Chronicles: The People, Passion, and Politics Behind Intel's Landmark Chips

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"The Pentium Chronicles" describes the architecture and key decisions that shaped the P6, Intel's most successful chip to date. As author Robert Colwell recognizes, success is about learning from others, and "Chronicles" is filled with stories of ordinary, exceptional people as well as frank assessm...

Author
Robert P. Colwell

Binding
Paperback

Pages
208

Publisher
Wiley-IEEE Computer Society Pr

ISBN #
0471736171

EAN Code
9780471736172

ISBN #
1

By Robert P. Colwell The Pentium Chronicles: The People, Passion, and Politics Behind Intel's Landmark Chips (1st Edition)

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Binding
Paperback

Publisher
Wiley-IEEE Computer Society Pr

EAN Code
8601403915643

ISBN #
5

Manual of remote sensing

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Manual Of Remote Sensing

Author
Robert N. Colwell

Binding
Hardcover

Pages
2440

Publisher
American Society of Photogrammetry

ISBN #
0937294411

EAN Code
9780937294413

ISBN #
4

Robert Colwell's guide to Snow Trails

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Author
Robert Colwell

Binding
Hardcover

Publisher
Stackpole Books

ISBN #
3

Classmates

Robert Colwell

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Schools:

Oxhead Road Elementary School Centereach NY 1964-1969, Ridge Elementary School Ridge NY 1968-1969, holy family diocesean high school Huntington NY 1977-1981

Community:

Keith Jaret

Robert Colwell

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Schools:

Johnston Elementary School Wilkinsburg PA 1949-1955, Wilkinsburg Junior High School Wilkinsburg PA 1955-1958

Community:

Dahrin Cook, Tommy Farineau

Robert Colwell

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Schools:

Golden Valley High School Golden Valley MN 1977-1981

Community:

Nystrom Fudge, Bruce Heideman, Pam Ansel

Robert Colwell

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Schools:

Emerson Junior High School West Los Angeles CA 1972-1974

Community:

Pam Cohen, Michael Burke, Peter Coyle

Robert Colwell

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Schools:

Princess Anne Elementary School Virginia Beach VA 1974-1975, North Landing Elementary School Virginia Beach VA 1975-1976, Oceanair Elementary School Norfolk VA 1976-1977, Titustown Elementary School Norfolk VA 1977-1978, Suburban Park Elementary School Norfolk VA 1978-1979, Gulfport Elementary School Gulfport FL 1979-1980, Azalea Middle School St. Petersburg FL 1980-1983

Community:

Chris Allison, Sarah Frank

Robert Colwell

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Schools:

Fort Crook Elementary School Bellevue NE 1975-1982, Mission Junior High School Bellevue NE 1982-1985

Community:

Christinne Jenkins, Karen Klein, Daniel Peek, Rebbeca Lynn, Edward Klein, Laura Logsdon, Yvonne Normandin, Marlene Knapp, Rosemary Delaney, Kim Murray

Robert Colwell

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Schools:

St. Michael's High School Henryetta OK 1948-1950

Community:

Richard Meadows, Frank Crawford, Judith Panchot, Dorothy Rutherford, Robert Barnett, Gene Williams, Charles Russell, Carroll Barvais, Mary Meadows, Thomas Patterson, Jennifer Kelch