Robert Bryan Dawson

US Patent:

6353253, Mar 5, 2002

Filed:

Jan 8, 1999

Appl. No.:

09/227914

Inventors:

Fred N. Hause - Austin TX
Basab Bandyopadhyay - Austin TX
Robert Dawson - Austin TX
Mark W. Michael - Cedar Park TX
William S. Brennan - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2900

US Classification:

257510, 257513

Abstract:

An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.

US Patent:

6372588, Apr 16, 2002

Filed:

Apr 21, 1997

Appl. No.:

08/837523

Inventors:

Derick J. Wristers - Austin TX
Robert Dawson - Austin TX
Mark I. Gardner - Cedar Creek TX
Frederick N. Hause - Austin TX
Mark W. Michael - Cedar Park TX
Bradley T. Moore - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438303, 438564

Abstract:

A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device region, forming a heavily doped diffusion source layer over the insulating layer, and driving a dopant from the diffusion source layer through the insulating layer into the gate and the device region by solid phase diffusion, thereby heavily doping the gate and forming a heavily doped source and drain in the device region. Preferably, the gate and diffusion source layer are polysilicon, the gate insulator and insulating layer are silicon dioxide, the dopant is boron or boron species, and the dopant provides essentially all P-type doping for the gate, source and drain, thereby providing shallow channel junctions and reducing or eliminating boron penetration from the gate into the substrate.

US Patent:

6376330, Apr 23, 2002

Filed:

Jun 5, 1996

Appl. No.:

08/655242

Inventors:

Robert Dawson - Austin TX
Fred N. Hause - Austin TX
Basab Bandyopadhyay - Austin TX
Mark W. Michael - Cedar Park TX
William S. Brennan - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2176

US Classification:

438421, 438422, 438619

Abstract:

A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.

US Patent:

6380055, Apr 30, 2002

Filed:

Oct 22, 1998

Appl. No.:

09/177043

Inventors:

Mark I. Gardner - Cedar Creek TX
Robert Dawson - Austin TX
Frederick N. Hause - Austin TX
Mark W. Michael - Cedar Park TX
Bradley T. Moore - Austin TX
Derick J. Wristers - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 213205

US Classification:

438585, 438560, 438592

Abstract:

A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilicon. The upper layer of polysilicon is doped more heavily than the lower layer of polysilicon, and the barrier region serves to keep most of the dopant within the upper layer of polysilicon, and yet may allow some of the dopant to diffuse into the lower layer of polysilicon. The barrier region may be formed, for example, by annealing the first polysilicon layer in an nitrogen-containing ambient to form a nitrided layer at the top surface of the first polysilicon layer. The barrier region may alternatively be formed by depositing a nitrogen-containing layer, such as a silicon nitride or titanium nitride layer, on the top surface of the first polysilicon layer. The thickness of the nitrogen-containing layer is preferably approximately 5-15 thick.

US Patent:

6399493, Jun 4, 2002

Filed:

May 17, 2001

Appl. No.:

09/860141

Inventors:

Robert Dawson - Austin TX
Jon D. Cheek - Round Rock TX
John G. Pellerin - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2144

US Classification:

438682, 438683, 438586, 438592

Abstract:

Various methods of fabricating a silicide film and structures incorporating the same are provided. In one aspect, a method of fabricating a silicide film is provided that includes providing a silicon surface and etching the silicon surface at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide. The roughing of the silicon surface facilitates metal-silicide reactions.

US Patent:

6410409, Jun 25, 2002

Filed:

Oct 31, 1996

Appl. No.:

08/741799

Inventors:

Mark I. Gardner - Cedar Creek TX
Robert Dawson - Austin TX
Frederick N. Hause - Austin TX
Mark W. Michael - Cedar Park TX
Bradley T. Moore - Austin TX
Derick J. Wristers - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21265

US Classification:

438526, 438527, 438528

Abstract:

Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier layer near the upper boundary of the P+ layer and well below transistor source/drain regions. One embodiment includes a lightly doped epitaxial layer formed upon an underlying P+ substrate. In another embodiment, a deep boron implant forms a P+ layer within a P- substrate, and affords many of the advantages of an epitaxial layer without actually requiring such an epitaxial layer. The nitrogen implant is performed at a preferred energy of 1-3 MeV to form the implanted nitrogen barrier layer at a depth in the range of 1-5 microns. Oxygen may also be implanted to form a diffusion barrier layer to retard the upward diffusion of arsenic or phosphorus forming a deep N+ layer.

US Patent:

6472751, Oct 29, 2002

Filed:

Sep 6, 2000

Appl. No.:

09/656437

Inventors:

Robert C. Chen - Los Altos CA
Jeffrey A. Shields - Sunnyvale CA
Robert Dawson - Austin TX
Khanh Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2940

US Classification:

257758, 257759, 257760, 257774, 257700, 257787, 257649, 257751, 438687, 438688, 438689

Abstract:

A dielectric interlayer is formed over a semiconductor substrate comprising at least one active region. The exposed upper surface of the dielectric interlayer is treated with nitrogen to form a nitrided barrier layer thereon. At least one hydrogen-containing dielectric layer is formed over the dielectric interlayer having the nitrided barrier layer thereon. The nitrided barrier layer serves as a barrier to diffusion of hydrogen from the at least one hydrogen-containing dielectric layer into the dielectric interlayer, thereby preventing a decrease in hot carrier injection reliability.

US Patent:

6522013, Feb 18, 2003

Filed:

Aug 19, 1998

Appl. No.:

09/136527

Inventors:

Robert C Chen - Los Altos CA
Jeffrey A. Shields - Sunnyvale CA
Robert Dawson - Austin TX
Khanh Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

257774, 257751, 257752, 257763

Abstract:

Punch-through vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an exposed upper surface of a lower metal feature, e. g. portions exposed by penetrating and undercutting an anti-reflective coating. A metal such as tungsten is subsequently deposited to fill the punch-through via. Embodiments include thermal decomposition of an organic-titanium compound, such as tetrakis-dimethylamino titanium, and treating the deposited titanium nitride in an H /N plasma to lower its resistivity. Moreover, the thickness of the anti-reflective coating can be reduced and the process window for etching the via widened.