Robert J Dawson

US Patent:

6353253, Mar 5, 2002

Filed:

Jan 8, 1999

Appl. No.:

09/227914

Inventors:

Fred N. Hause - Austin TX
Basab Bandyopadhyay - Austin TX
Robert Dawson - Austin TX
Mark W. Michael - Cedar Park TX
William S. Brennan - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2900

US Classification:

257510, 257513

Abstract:

An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.

US Patent:

6372588, Apr 16, 2002

Filed:

Apr 21, 1997

Appl. No.:

08/837523

Inventors:

Derick J. Wristers - Austin TX
Robert Dawson - Austin TX
Mark I. Gardner - Cedar Creek TX
Frederick N. Hause - Austin TX
Mark W. Michael - Cedar Park TX
Bradley T. Moore - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438303, 438564

Abstract:

A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device region, forming a heavily doped diffusion source layer over the insulating layer, and driving a dopant from the diffusion source layer through the insulating layer into the gate and the device region by solid phase diffusion, thereby heavily doping the gate and forming a heavily doped source and drain in the device region. Preferably, the gate and diffusion source layer are polysilicon, the gate insulator and insulating layer are silicon dioxide, the dopant is boron or boron species, and the dopant provides essentially all P-type doping for the gate, source and drain, thereby providing shallow channel junctions and reducing or eliminating boron penetration from the gate into the substrate.

US Patent:

6376330, Apr 23, 2002

Filed:

Jun 5, 1996

Appl. No.:

08/655242

Inventors:

Robert Dawson - Austin TX
Fred N. Hause - Austin TX
Basab Bandyopadhyay - Austin TX
Mark W. Michael - Cedar Park TX
William S. Brennan - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2176

US Classification:

438421, 438422, 438619

Abstract:

A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.

US Patent:

6399493, Jun 4, 2002

Filed:

May 17, 2001

Appl. No.:

09/860141

Inventors:

Robert Dawson - Austin TX
Jon D. Cheek - Round Rock TX
John G. Pellerin - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2144

US Classification:

438682, 438683, 438586, 438592

Abstract:

Various methods of fabricating a silicide film and structures incorporating the same are provided. In one aspect, a method of fabricating a silicide film is provided that includes providing a silicon surface and etching the silicon surface at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide. The roughing of the silicon surface facilitates metal-silicide reactions.

US Patent:

6552776, Apr 22, 2003

Filed:

Oct 30, 1998

Appl. No.:

09/183176

Inventors:

Derick J. Wristers - Austin TX
Robert Dawson - Austin TX
Mark I. Gardner - Cedar Creek TX
Frederick N. Hause - Austin TX
Bradley T. Moore - Austin TX
Mark W. Michael - Cedar Park TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03B 2754

US Classification:

355 67, 355 71

Abstract:

A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.

US Patent:

6661057, Dec 9, 2003

Filed:

Apr 7, 1998

Appl. No.:

09/056836

Inventors:

Robert Dawson - Austin TX 78730
Mark I. Gardner - Cedar Creek TX 78612
Frederick N. Hause - Austin TX 78749
Mark W. Michael - Cedar Park TX 78613
Bradley T. Moore - Austin TX 78746
Derick J. Wristers - Austin TX 78728

International Classification:

H01L 27088

US Classification:

257336, 257344, 257408, 257900, 438306

Abstract:

A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.

US Patent:

6677647, Jan 13, 2004

Filed:

Sep 15, 1998

Appl. No.:

09/153807

Inventors:

Robert Dawson - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2972

US Classification:

257368, 257763, 257764, 257765, 257767, 438656, 438669, 438672

Abstract:

The electromigration characteristics of patterned metal features, such as metal lines, in semiconductor devices is improved by applying a conductive layer to substantially surround and encapsulate the patterned metal features. A portion of the conductive layer may be removed to form conductive sidewall spacers on the side surfaces of the patterned metal features. In an embodiment of the invention, the conductive layer comprises a first layer of titanium and a second layer of titanium-nitride thereon.

US Patent:

6977195, Dec 20, 2005

Filed:

Aug 16, 2004

Appl. No.:

10/919119

Inventors:

John J. Bush - Leander TX, US
Wen-Jie Qi - Austin TX, US
Robert Dawson - Austin TX, US

Assignee:

FASL, LLC - Sunnyvale CA

International Classification:

H01L021/336
H01L021/8234

US Classification:

438197, 438224, 438227

Abstract:

For characterizing bulk leakage current of a junction, a center junction surrounded by an isolation structure is formed with a first depth. In addition, at least one periphery junction having a second depth greater than the first depth is formed in a portion of the center junction adjacent the isolation structure. A junction silicide is formed with the center and periphery junctions. The magnitude of a reverse-bias voltage across the junction silicide and the P-well is incremented for determining a critical magnitude of the reverse-bias when current through the junction silicide and the P-well reaches a threshold current density.