Robert S Day

US Patent:

6544584, Apr 8, 2003

Filed:

Mar 7, 1997

Appl. No.:

08/813765

Inventors:

Edward Lee Arrington - Owego NY
John Christopher Camp - Owego NY
Robert Jeffrey Day - Dryden NY
Edmond Otto Fey - Vestal NY
Curtis Michael Gunther - Apalachin NY
Thomas Richard Miller - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B05D 512

US Classification:

427 96, 427 98, 427304, 427337, 427437, 4274431

Abstract:

A process for removal of undesirable conductive material (e. g. , catalyst material and seeped circuit material) on a circuitized substrate and the resultant circuitized substrates disclosed. Such process and resultant circuit effectively address the electrical shorting problems caused by nonremoval of the residual catalyst material and circuit material which has seeped under the residual catalyst material. The process includes the steps of: a) providing a catalyst layer (e. g. , palladium and tin) having circuit pattern (e. g. , copper) thereon; b) pretreating the catalyst layer and the circuit pattern (e. g. , with a cyanide dip) for removal of undesirable portions of each which cause electrical leakage between circuit lines of the circuit pattern; c) oxidizing the catalyst layer and the circuit pattern (e. g. , with chlorite, permanganate, hydrogen peroxide, or air at a temperature elevated above ambient conditions); and d) removing the undesirable portions of the catalyst layer and the undesirable portions of the circuit pattern (e. g. , with a cyanide submersion).

US Patent:

6775907, Aug 17, 2004

Filed:

Sep 14, 2000

Appl. No.:

09/661738

Inventors:

Christina M. Boyko - Endicott NY
Robert J. Day - Dryden NY
Kristen A. Stauffer - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01K 310

US Classification:

29852, 29846, 427 96, 427 97

Abstract:

The present invention teaches a simplified process for fabricating high density printed wiring boards using a semi-additive process. Steps required to achieve this objective include adhering an electroless plated copper commoning layer to a surface roughened dielectric substrate. Subsequently, the commoning layer is photolithographically personalized by covering the commoning layer with a resist and then uncovering predetermined areas of the aforementioned commoning layer. Consequently, the semi-additive method involves electroplating copper onto the uncovered areas of the commoning layer, thereby generating copper features and circuitry. Finally, the semi-additive process requires the stripping of the remaining photoresist, and the unplated electroless copper layer is etched in order to electronically isolate the copper features and circuitry lines.

US Patent:

62127691, Apr 10, 2001

Filed:

Jun 29, 1999

Appl. No.:

9/343077

Inventors:

Christina M. Boyko - Endicott NY
Robert J. Day - Dryden NY
Kristen A. Stauffer - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 330

US Classification:

29852

Abstract:

The present invention teaches a simplified process for fabricating high density printed wiring boards using a semi-additive process. A roughened copper foil is laminated to a dielectric substrate. The foil is subsequently removed from the dielectric to create a roughened, irregular surface on the dielectric substrate. Vertical angle through holes and blind holes are formed in the substrate. A uniform copper commoning layer is electrolessly plated to the roughened dielectric substrate and through holes. A photoresist is applied on the surface of the electroless plated layer and irradiated through a mask having printed circuit features. After developing the photoresist the uncovered electroless layer is electrolytically plated to create the final features and circuitry. After stripping the remaining photoresist the unplated electroless copper layer is etched to electronically isolate the copper features and circuitry lines.

US Patent:

53116607, May 17, 1994

Filed:

Feb 10, 1993

Appl. No.:

8/015742

Inventors:

Warren A. Alpaugh - Chenango Forks NY
Anilkumar C. Bhatt - Johnson City NY
Michael J. Canestaro - Endicott NY
Robert J. Day - Dryden NY
Edmond O. Fey - Vestal NY
John E. Larrabee - Conklin NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01K 310

US Classification:

29852

Abstract:

Disclosed is a method of drilling, desmearing, and additively circuitizing a printed circuit board. The printed circuit board is drilled under conditions which produce glass and polymer smeared vias and through holes. The particulate debris is removed by vapor blasting the drilled printed circuit board. Next the printed circuit board is soaked in a solvent to swell the drill smear on the circuit interplanes of the printed circuit board. This solvent is then removed by entrainment in a gas, and a stream of an aqueous, acidic, oxidizing solution is passed through the printed circuit board holes to remove swollen smear in the thru holes and produce an etchback of conductors. After a water rinse an aqueous reducing solution is passed through the printed circuit board to reduce and remove aqueous acidic oxidizing solution, e. g. , residual aqueous acid oxidizing solution. The printed circuit board is rinsed to remove the aqueous reducing solution.

US Patent:

57078939, Jan 13, 1998

Filed:

Dec 1, 1995

Appl. No.:

8/566363

Inventors:

Anilkumar Chinuprasad Bhatt - Johnson City NY
Ashwinkumar Chinuprasad Bhatt - Endicott NY
Robert Jeffrey Day - Dryden NY
Thomas Patrick Duffy - Endicott NY
Jeffrey Alan Knight - Endwell NY
Richard William Malek - Johnson City NY
Voya Rista Markovich - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21445

US Classification:

437195

Abstract:

A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e. g. , additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e. g. , high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.

US Patent:

58174052, Oct 6, 1998

Filed:

Feb 4, 1997

Appl. No.:

8/795180

Inventors:

Anikumar Chinuprasad Bhatt - Johnson City NY
Ashwinkumar Chinuprasad Bhatt - Endicott NY
Robert Jeffrey Day - Dryden NY
Thomas Patrick Duffy - Endicott NY
Jeffrey Alan Knight - Endwell NY
Richard William Malek - Johnson City NY
Voya Rista Markovich - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 900

US Classification:

428209

Abstract:

A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e. g. , additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e. g. , high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.

US Patent:

60634812, May 16, 2000

Filed:

Mar 6, 1998

Appl. No.:

9/036065

Inventors:

Edward Lee Arrington - Owego NY
John Christopher Camp - Owego NY
Robert Jeffrey Day - Dryden NY
Edmond Otto Fey - Vestal NY
Curtis Michael Gunther - Apalachin NY
Thomas Richard Miller - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 300
B32B 1504

US Classification:

428209

Abstract:

A process for removal of undesirable conductive material (e. g. , catalyst material and seeped circuit material) on a circuitized substrate and the resultant circuitized substrates disclosed. Such process and resultant circuit effectively address the electrical shorting problems caused by nonremoval of the residual catalyst material and circuit material which has seeped under the residual catalyst material. The process includes the steps of: a) providing a catalyst layer (e. g. , palladium and tin) having circuit pattern (e. g. , copper) thereon; b) pretreating the catalyst layer and the circuit pattern (e. g. , with a cyanide dip) for removal of undesirable portions of each which cause electrical leakage between circuit lines of the circuit pattern; c) oxidizing the catalyst layer and the circuit pattern (e. g. , with chlorite, permanganate, hydrogen peroxide, or air at a temperature elevated above ambient conditions); and d) removing the undesirable portions of the catalyst layer and the undesirable portions of the circuit pattern (e. g. , with a cyanide submersion).

Address:

5900 Allegheny Rd, Williamsburg, VA 23188

VIN:

1N4AL21E37N405791

Make:

NISSAN

Model:

ALTIMA

Year:

2007