2201 south Mcdowell Boulevard Ext, Petaluma, CA 94954
Industry:
Semiconductors
Work:
Wheatstone Ip Law Corporation
Senior Ip Technologist
Tegal Corporation Apr 2011 - Oct 2012
Chief Technologist
Tegal Corporation Nov 2008 - Apr 2011
Director of Research and Development and Ip Manager
Tegal Corporation 2003 - 2008
Manager of Etch Process
Tegal Corporation Oct 1992 - Oct 2002
Senior Process Engineer
Education:
Sonoma State University 1997 - 2001
Master of Business Administration, Masters, Business Administration, Management, Business Administration and Management
Penn State University 1983 - 1993
Master of Science, Doctorates, Bachelors, Masters, Doctor of Philosophy, Bachelor of Science, Engineering
Williamson School of Mechanical Trades 1980 - 1983
Skills:
R&D Semiconductors Thin Films Semiconductor Manufacturing Product Development Research Strategic Planning Intellectual Property Patent Preparation Semiconductor Process Engineering Management Characterization Plasma Etch Design of Experiments Manufacturing Process Simulation Management Electronics Semiconductor Industry Patents Semiconductor Fabrication Solar Energy Nanotechnology Start Ups Plasma Physics Program Management Plasma Etching Cross Functional Team Leadership Materials Science Process Engineering Product Management Mems Engineering
Stephen P. DeOrnellas - Petaluma CA Robert A. Ditizio - Petaluma CA
Assignee:
Tegal Corporation - Petaluma CA
International Classification:
C23C 1600
US Classification:
118723E, 156345
Abstract:
A reactor includes a shield which prevents the deposition of materials along a line-of-sight path from a wafer toward and onto an electrode , or a window which couples an electrode to a reaction chamber of the reactor. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.
Stephen P. DeOrnellas - Santa Rosa CA Robert A. Ditizio - Petaluma CA
Assignee:
Tegal Corporation - Petaluma CA
International Classification:
C23C 1600
US Classification:
1563453, 15634547, 118723 E, 118504
Abstract:
A rotary transformer includes a resonant circuit and a coil drive circuit. The resonant circuit includes a resonating capacitor connected to a power MOS transistor, coupled across the primary coil of the transformer. The coil drive circuit includes a diode connected to a power MOS transistor coupled across the primary coil of the transformer. A microprocessor detects changes in the voltage across the primary coil. The resonant circuit is connected and disconnected from the transformer during a power transfer mode and a data transfer mode, respectively. During the power transfer mode, stored energy in the leakage inductance of the primary coil is used for power coupling, via the resonant circuit, instead of being dissipated as heat. The resonant circuit is disconnected from the rotary transformer during the data transfer mode to maximize bandwidth for two-way data transfer between the primary and secondary sides of the transformer. The transformer uses a synchronous mode of operation in which the power MOS transistor of the coil drive circuit is turned on when the voltage across the primary coil changes from a positive to a negative value during the power transfer mode.
System And Method For Processing A Wafer Including Stop-On-Aluminum Processing
Magnetic tunnel junction (MTJ) devices can be fabricated by a stop-on-alumina process whereby the tunnel junction layer serves as the stop layer during plasma overetching of the upper magnetic layer. The resulting side walls of the MTJ device are non-vertical in the vicinity of the tunnel junction layer which serves to electrically isolate the upper magnetic layer from the lower magnetic layer. The gas employed during plasma overetching excludes halogen containing species which results in highly selective etching of the magnetic layer vis-à-vis the alumina tunnel barrier layer. The introduction of oxygen in the gas may enhance the reproducibility of the overetch process. Finally, plasma treatment with He and Hfollowed by rinsing and baking subsequent to removal of the photoresist mask during the fabrication process enhances yield.
Dry Etch Stop Process For Eliminating Electrical Shorting In Mram Device Structures
The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.
Dry Etch Stop Process For Eliminating Electrical Shorting In Mram Device Structures
The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.
System And Method For Processing A Wafer Including Stop-On-Alumina Processing
Magnetic tunnel junction (MTJ) devices can be fabricated by a stop-on-alumina process whereby the tunnel junction layer serves as the stop layer during plasma overetching of the upper magnetic layer. The resulting side walls of the MTJ device are non-vertical in the vicinity of the tunnel junction layer which serves to electrically isolate the upper magnetic layer from the lower magnetic layer. The gas employed during plasma overetching excludes halogen containing species which results in highly selective etching of the magnetic layer vis-à-vis the alumina tunnel barrier layer. The introduction of oxygen in the gas may enhance the reproducibility of the overetch process. Finally, plasma treatment with He and Hfollowed by rinsing and baking subsequent to removal of the photoresist mask during the fabrication process enhances yield.
Robert Ditizio - Petaluma CA, US Steve Selbrede - Novato CA, US
International Classification:
H01L 21/20
US Classification:
438396000
Abstract:
The present invention discloses a fabrication process for integrated high dielectric constant capacitors for circuit decoupling. The top electrode is protected against the re-deposition of material from the bottom electrode during the patterning process of the bottom electrode, thus provides better capacitor yield against the shortage of top and bottom electrodes. The protection can be a sidewall spacer, or an extra hard mask protecting the sidewall of the top electrode. The dielectric for the decoupling capacitors is preferably novel high dielectric constant materials such as (BaCa)(TiZr)O(BCTZ). The used of novel BCTZ high dielectric constant materials requires compatible electrode or seed layer such as Au or NiV, plus a low power etching process to avoid material damage.
Robert Anthony Ditizio - Petaluma CA, US Tue Nguyen - Fremont CA, US Tai Dung Nguyen - Fremont CA, US
Assignee:
TEGAL CORPORATION - Petaluma CA
International Classification:
H05H 1/00
US Classification:
427569, 977891
Abstract:
A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, comprising introducing a first plurality of precursors to deposit a thin layer with the deposition process not self limiting, followed by introducing a second plurality of precursors for plasma treating the thin deposited layer. The plasma can be isotropic, anisotropic, or a combination of isotropic and anisotropic to optimize the effectiveness of the treatment of the thin deposited layers.