Robert Wayne Dotson

US Patent:

6759891, Jul 6, 2004

Filed:

Apr 29, 2002

Appl. No.:

10/133761

Inventors:

Robert N. Dotson - Chandler AZ

Assignee:

Semiconductor Components Industries, L.L.C. - Phoenix AZ

International Classification:

G05F 326

US Classification:

327512, 327361, 327540, 361103, 323315

Abstract:

An integrated circuit ( ) includes a thermal shutdown circuit that incorporates hysteresis for shutting down a functional circuit ( ) when its temperature exceeds a predefined value. First and second current sources ( ) respectively produce first and second reference currents (I , I ) representative of first and second die temperatures of the integrated circuit. A current mirror ( ) has an input ( ) for summing the first and second reference currents and an output ( ) for providing a mirror current (I ). A detection circuit ( ) has an output coupled to the output of the current mirror for sinking the mirror current to produce a detection signal (V ) as a function of the first and second die temperatures.

US Patent:

57265976, Mar 10, 1998

Filed:

Aug 30, 1996

Appl. No.:

8/706095

Inventors:

Thomas D. Petty - Tempe AZ
Richard S. Griffith - Chandler AZ
Robert L. Vyne - Tempe AZ
Robert N. Dotson - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 522

US Classification:

327307

Abstract:

A trim circuit (10) and method of reducing offset voltages in a differential input stage. The differential input transistors (32 and 42) have separate bulk terminals for receiving a voltage to compensate for the input offset voltage. A current source (60) supplies a static current to the offset compensation circuit for generating a bias voltage at node (55). The transistors (64 and 66) receive a voltage at input terminals (30 and 40) and supply an additional current to an offset compensation circuit (20). A switch circuit (50) has switch pairs (52, 56, and 54, 58) for transferring a voltage to the bulk terminal of one of the differential transistors (32 and 42) while grounding the bulk terminal of the other transistor. The differential voltage supplied across the bulk terminals of transistors (32 and 42) changes the threshold voltage of the transistors reducing the offset voltage of the input stage.

US Patent:

44853521, Nov 27, 1984

Filed:

Aug 30, 1982

Appl. No.:

6/413052

Inventors:

Robert B. Davies - Tempe AZ
Robert N. Dotson - Mesa AZ
Michael W. Null - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 304

US Classification:

330288

Abstract:

A current amplifier uses a current mirror arrangement as an operational amplifier whose output has limited swing. The limited swing is achieved through a plurality of series connected diodes connected to a control input of the amplifier and to the output of the operational amplifier. The control input is coupled through a transistor to inhibit the output of the current mirror arrangement. The output node is coupled to an output for the current amplifier through a Darlington arrangement which provides high current gain.

US Patent:

57342962, Mar 31, 1998

Filed:

Mar 19, 1996

Appl. No.:

8/618671

Inventors:

Robert N. Dotson - Chandler AZ
Richard S. Griffith - Chandler AZ
Robert L. Vyne - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 345
H03F 316

US Classification:

330253

Abstract:

Low voltage operational amplifier (10) operates in a voltage range of one to eight volts over a temperature range of 0. degree. to 70. degree. centigrade. Op amp input stage (12) uses N-channel depletion-mode MOSFETs to provide amplification of the differential input and maintain constant transconductance. Source follower MOSFET (13) provides unity gain in transferring the AC signal, STAGE-1 OUTPUT, to the base of current sinking transistor (18). Sink control circuit (14) and source control circuit (22) generate the base drive currents for transistors (18) and (24). The signal at the output of MOSFET (13) either causes the sink transistor (18) to sink current or the signal to be transposed by means of a translinear loop (16) and causes the source transistor (24) to source current. An output stage provides approximately fifty milliamps of current drive and is quiescent until the output driver is selected.

US Patent:

45544646, Nov 19, 1985

Filed:

Aug 30, 1982

Appl. No.:

6/413051

Inventors:

Robert B. Davies - Tempe AZ
Ira Miller - Tempe AZ
Robert N. Dotson - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 3017
H03K 504
H03K 1756

US Classification:

307265

Abstract:

A propagation delay generator is provided for controlling the duration of a bubble generate waveform of a bubble memory system. A first means is responsive to a digital input signal and provides an initializing signal to a current source. A capacitor is charged, responsive to an R-C time constant, by an increased voltage level prompted by the initializing signal. A second means is responsive to the charging signal in excess of that required to charge the capacitor. The second means thereby provides a digital output that is delayed from the digital input signal.

US Patent:

43386466, Jul 6, 1982

Filed:

Apr 27, 1981

Appl. No.:

6/257837

Inventors:

William F. Davis - Tempe AZ
Robert N. Dotson - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H02H 308

US Classification:

361 18

Abstract:

A current limiting circuit is provided wherein the monitored voltage is applied to the base of first and second transistors, the first transistor having a substantially larger emitter area than the second transistor. Impedance means are connected to the emitters of the first and second transistors such that they function in conjunction with the emitter area ratio causing the current flowing through the first transistor to be higher than that flowing through the second transistor at low base voltages, while at higher base voltages the current flowing through the second transistor is higher than flowing through the first transistor. At some intermediate voltage the current flowing through both the first and second transistors is equal. This property may be used, for example, in a voltage regulator so as to divert base drive current from the output transistor at the point where the first and second currents are equal.

US Patent:

44764294, Oct 9, 1984

Filed:

Aug 27, 1982

Appl. No.:

6/412070

Inventors:

Ira Miller - Tempe AZ
Robert N. Dotson - Mesa AZ
Robert B. Davies - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G05F 500

US Classification:

323299

Abstract:

A circuit for providing the gate of a bubble memory with a precision current pulse at a high voltage is manufactured using a low voltage process; i. e. BV. sub. ceo is approximately 18 volts. In order to accomplish this, first and second voltage level shifting stages are cascoded and the output transistors thereof are used as Zener level shifters each level shifting downward by a BV. sub. ceo when only a small voltage is dropped across the load. If the voltage drop across the load increases, the cascoded output transistors may enter their active region and are prevented from going into saturation by saturation clamps so as to not introduce unwanted delays in the rise or fall times of the current pulse.

US Patent:

44853190, Nov 27, 1984

Filed:

Feb 26, 1982

Appl. No.:

6/352989

Inventors:

Robert B. Davies - Tempe AZ
Robert N. Dotson - Mesa AZ
Ira Miller - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 5159
H03K 1700
G11C 1908

US Classification:

307530

Abstract:

A sense amplifier which is fully integrated has an on-chip voltage regulator to provide essentially error free operation. The sense amplifier provides peak-to-peak signal detection for comparison to a threshold voltage by a comparator. The output of the comparator is coupled to an RS flip-flop. The output of the RS flip-flop is coupled to a D flip-flop. The use of an RS flip-flop as well as a D flip-flop eliminates clocking problems caused by skewing and keeps a stored detected signal from changing prematurely.