Robert L Douglas

US Patent:

6463506, Oct 8, 2002

Filed:

Apr 29, 2000

Appl. No.:

09/562592

Inventors:

Curtis R. McAllister - Sunnyvale CA
Robert C. Douglas - Santa Clara CA
Henry Yu - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711118, 711 3, 711145, 711144

Abstract:

A memory system includes a main memory controller supplying data in response to transactions received by the main memory controller. A plurality of modules each include a cache memory for storing data supplied by the main memory controller. The modules request data from the main memory controller by sending module generated transactions to the main memory controller. A cache tag array includes a cache tag corresponding to each data line stored in memory, there being a one-to-one correspondence between the cache tags and the data lines. The data lines together with their associated cache tags are combined and arranged in a plurality of sequential data chunks, the cache tags included in an initial portion of the data chunks (i. e, a first sequence of bits) followed by inclusion of the data lines in a subsequent portion of the data chunks (i. e. , the usable bit positions following inclusion of all of the cache tag bits.

US Patent:

6598140, Jul 22, 2003

Filed:

Apr 30, 2000

Appl. No.:

09/560927

Inventors:

Curtis R. McAllister - Sunnyvale CA
Robert C. Douglas - Santa Clara CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1208

US Classification:

711168, 711141, 711154, 711152, 709102, 710107, 710 39

Abstract:

A memory controller has separate memory controller agents that process memory transactions in parallel. A memory controller in accordance with the present invention includes a plurality of memory controller agents, which are coupled to each other via a series of busses, an incoming memory transaction dispatch unit, and an outgoing memory dispatch unit. Memory transactions are received from cacheable entities of a computer system at the incoming memory transaction dispatch unit, and are then presented to the plurality of agents. For each incoming transaction, one of the agents will accept the transaction. Each agent is responsible for ensuring coherency and fulfilling memory transactions for a single memory line. If multiple memory read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests. The coherency information and memory line data associated with each memory line may be cached by each agent, thereby allowing repeated requests to the same memory line to be serviced more quickly.

US Patent:

6611906, Aug 26, 2003

Filed:

Apr 30, 2000

Appl. No.:

09/560928

Inventors:

Curtis R. McAllister - Sunnyvale CA
Robert C. Douglas - Santa Clara CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1208

US Classification:

711168, 711141, 711154, 711152, 709102, 710107, 710 39

Abstract:

A hardware-based linked list queues memory transactions in a memory controller. The memory controller includes a plurality of memory controller agents. Each agent has a head flag, a tail flag, and a next agent field, thereby allowing the agents to be arranged into linked lists. Memory transactions are received from cacheable entities of a computer system at an incoming memory transaction dispatch unit via an interconnection fabric. The incoming transactions are then presented to the plurality of agents. For each incoming read transaction, one of the agents will accept the transaction. If there are pending memory read transactions for the memory line, then the accepting agent joins a linked list of agents that are queued up to access that memory line. The accepting agent drives its index out onto a bus that connects all agents. One agent in the linked list will have its tail flag set, and that agent will clear its tail flag and latch into its next agent field the index provided by the accepting agent.

US Patent:

6928520, Aug 9, 2005

Filed:

May 14, 2003

Appl. No.:

10/437677

Inventors:

Curtis R. McAllister - Sunnyvale CA, US
Robert C. Douglas - Santa Clara CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F012/08

US Classification:

711141, 711138, 711144

Abstract:

Embodiments of the present invention include a memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent. The memory controller includes at least one memory-controller agent, an incoming memory-transaction dispatch unit, and an outgoing memory-transaction completion unit. Each memory-controller agent has a memory-line memory controller and a memory-line coherency controller, along with a cache memory capable of caching the contents of a memory line along with coherency information for the memory line. Memory transactions are received from cacheable entities of a computer system at the incoming memory-transaction dispatch unit, and are then presented to one or more agents. If multiple memory-read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests.

US Patent:

7028150, Apr 11, 2006

Filed:

Aug 23, 2002

Appl. No.:

10/226418

Inventors:

Curtis R. McAllister - Sunnyvale CA, US
Robert C. Douglas - Santa Clara CA, US
Henry Yu - San Jose CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

711156, 711129, 711141, 711144, 711170, 714766, 714768, 714777

Abstract:

A memory system and method for processing a data structure comprising a plurality of data bits representing a line of memory, wherein the data bits are divided into a plurality of data chunks, each of the data chunks including at least an error correction code portion and a data portion; and a first chunk of said plurality of data chunks having a tag portion, wherein said tag portion includes tag information for the entire line of memory, and wherein subsequent ones of said data chunks do not include tag information.

US Patent:

20210063184, Mar 4, 2021

Filed:

Aug 30, 2019

Appl. No.:

16/557856

Inventors:

- Plano TX, US
Robert Douglas - Frisco TX, US
Evan Vijithakumara - Frisco TX, US
Alex Pham - San Jose CA, US
Nutonya Lynn Parker - Dallas TX, US
Sriranjan Tadimari - Plano TX, US

International Classification:

G01C 21/34
G08G 1/01
G08G 1/052
G08G 1/14

Abstract:

Methods, systems, and apparatus for an event navigation system. The event navigation system includes a sensor configured to monitor traffic flow within a first structure. The event navigation system includes a memory configured to store a map of the first structure. The event navigation system includes a processor coupled to the sensor and the memory. The processor is configured to obtain a current location of a user and a destination location for the user. The processor is configured to determine a route from the current location to the destination location based on the map of the first structure, the current location, the destination location and the traffic flow within the first structure. The processor is configured to provide the route to the user.