Robert W Douglas

US Patent:

20060145654, Jul 6, 2006

Filed:

Jan 6, 2005

Appl. No.:

11/030684

Inventors:

Robert Douglas - Shillington PA, US

International Classification:

H02J 7/00

US Classification:

320104000

Abstract:

A system and method are disclosed for charging the liftgate batteries on a trailer having a trailer electrical system such as a refrigeration unit, from the charging system for the trailer electrical system. The system and method include an electrical connection between the liftgate batteries and the trailer electrical system alternator, wherein the trailer electrical system alternator has current capacity sufficient to power the trailer electrical system and to charge the liftgate batteries and the refrigeration unit battery; and an electrical isolation circuit for isolating the liftgate batteries from the trailer electrical system battery to prevent current from flowing from the trailer electrical system battery to the liftgate batteries.

US Patent:

50974696, Mar 17, 1992

Filed:

Nov 21, 1990

Appl. No.:

7/616735

Inventors:

Robert H. Douglas - Phoenix AZ

Assignee:

Concord Communications, Inc. - Marlboro MA

International Classification:

G06F 1100
H04J 300

US Classification:

371 201

Abstract:

The invention is a network monitor that passively detects sequences of control frame transmissions. Detected control frame sequences are compared to a model of the expected exchange of control frames. The monitor concludes that a malfunction has occurred when the detected control frame sequences do not match the frame sequences indicated by model. The monitor is quite useful with a network that uses a token passing protocol, since it can determine whether a particular station is working improperly by tracking whether the token is passed in the order proscribed by the expected token-passing sequence in the model. The monitor can detect and diagnose many types of network malfunctions. The monitor also observes and maintains statistics on network data traffic and configuration information, in real time. Since the monitor independently tracks which station has the token, statistics are developed on how much traffic is passing to and from bridges.

US Patent:

40842339, Apr 11, 1978

Filed:

May 25, 1976

Appl. No.:

5/689822

Inventors:

Robert J. Handly - Phoenix AZ
Robert H. Douglas - Phoenix AZ

Assignee:

Honeywell, Inc. - Minneapolis MN

International Classification:

G06F 900
H03K 326
H03K 1920
H03K 513

US Classification:

364200

Abstract:

A computer system features a processor unit which includes its own microprogram control unit. The microprogram control unit includes a storage means for operational instructions for the processor unit and means to issue those instructions in a desired sequence. A communication Bus provides communication channels between the processor unit and either data storage means or other processor units served by the Bus. The processor unit includes a number of clock controlled functional components as well as means for requesting access to the Bus. A clock signal generating means is controlled by signals from the microprogram control unit. When a request has been made for access to the Bus, the processor continues to operate until a point is reached when access to the Bus must be accomplished before continuing. The microprogram control unit issues a control signal which effectively stops the operation of the clock signal generating means until the Bus access routine has been accomplished. The clock signal generating means resumes operation when the access routine has been completed.

US Patent:

42176573, Aug 12, 1980

Filed:

Oct 18, 1978

Appl. No.:

5/952562

Inventors:

Robert J. Handly - Phoenix AZ
Robert H. Douglas - Phoenix AZ

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

G06F 748

US Classification:

364748

Abstract:

An improved means and method for accomplishing floating point calculations in computational apparatus includes a primary microprocessor and a secondary microprocessor each with its own control ROM. The normal or fixed point calculations are handled by the primary microprocessor under the control of a first segment of the associated control ROM. When a floating point calculation is called for, a second segment of that ROM is addressed. The addressing of the second segment of the first ROM also effects the coincident addressing of the ROM of the secondary microprocessor. For floating point calculations, the exponent portion of the numbers being manipulated is handled in the primary microprocessor. Simultaneously therewith, the mantissa portion of the numbers being manipulated are handled in the secondary microprocessor under the control of its associated control ROM. The resultant calculations are recombined in the primary microprocessor to produce a complete solution for the floating point calculation.

US Patent:

41875389, Feb 5, 1980

Filed:

Jun 13, 1977

Appl. No.:

5/805963

Inventors:

Robert H. Douglas - Phoenix AZ
Thomas L. Phinney - Phoenix AZ

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

G06F 1300

US Classification:

364200

Abstract:

There is provided, in accordance with the present invention, apparatus comprising a shared random access memory in which is stored requests for access to data in a bulk memory unit. The data being stored in redundant storage areas and the requests stored in the RAM include the address of the redundant data. Means are provided for determining if that data request is already in progress through one of the redundant addresses. The first of the addresses accessed causes the others to be blocked to prevent multiple accessing of the same data. The checking and selection is accomplished by high speed logic circuitry.

US Patent:

42649536, Apr 28, 1981

Filed:

Mar 30, 1979

Appl. No.:

6/025679

Inventors:

Robert H. Douglas - Phoenix AZ
Thomas L. Phinney - Phoenix AZ

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

G06F 1516
G06F 1300

US Classification:

364200

Abstract:

A computer system includes a main memory and a cache memory arrangement, wherein a cache memory unit is associated with each of the several CPU's in the system. Each cache responds to the virtual address signals issued by the associated CPU, in parallel with a mapper unit which, in turn, converts the virtual address signals to physical address signals for addressing the main memory. The cache is subdivided into subunits each responding to a particular program of a multiprogram CPU. When any of the CPUs address a shared portion of the main memory, the mapper unit recognizes the address of the shared portion of the main memory and issues an inhibit signal to inhibit the operation of the cache memory unit to prevent data from the shared portion of the main memory from being stored in the cache.

US Patent:

40630811, Dec 13, 1977

Filed:

Jun 8, 1976

Appl. No.:

5/693857

Inventors:

Robert J. Handly - Phoenix AZ
Robert H. Douglas - Phoenix AZ

Assignee:

Honeywell - Fort Washington PA

International Classification:

G06F 920
G11C 2900

US Classification:

235312

Abstract:

A computer apparatus includes means for comparing the address stored in an address register with a preset address. When the stored address matches the preset address the comparison means issues an alarm signal which may be used to effect an immediate halt in the execution of a routine, trigger suitable annunciators or, selectively, to enable the injection into the routine of an overriding preset instruction.

US Patent:

41174593, Sep 26, 1978

Filed:

Jun 2, 1977

Appl. No.:

5/802873

Inventors:

Robert H. Douglas - Phoenix AZ
Edward H. Forrester - Phoenix AZ
David Murray - Phoenix AZ

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H04Q 100

US Classification:

340147R

Abstract:

There has been provided, in a computer system, a control unit having authority over a plurality of subordinate units with differing response times. The control unit addresses and issues command instructions to selected ones of the subordinate units then waits for an acknowledgement of completion from the addressed units before going to the next step in its routine. To prevent the control unit from being hung-up in the event of a failure of response from the subordinate unit, time-out means are provided for releasing the control unit for further operation. Since the response times of the individual subordinate units are unknown to the control unit, a unique time-out circuit is provided for each of the subordinate units, each time-out circuit being commensurate with the response time of the associated subordinate unit.