Robert Joseph Farrell

US Patent:

6785829, Aug 31, 2004

Filed:

Jun 30, 2000

Appl. No.:

09/608160

Inventors:

Varghese George - Folsom CA
Robert L. Farrell - Gold River CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 132

US Classification:

713320, 713300, 713322, 713324, 713600

Abstract:

A power control circuit an corresponding technique for adjusting operating frequency and/or supply voltage in sections of a single electronic device while maintaining substantially constant operating frequency and/or supply voltage in the other sections in the electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is connected to an external power source. As a result, the electronic device in the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage in some sections of the processor and not in the other sections during other situations.

US Patent:

7249243, Jul 24, 2007

Filed:

Aug 6, 2003

Appl. No.:

10/636146

Inventors:

Mohammad A. Abadallah - Folsom CA, US
Mitchell Diamond - Folsom CA, US
David B. Jackson - Folsom CA, US
Kip A. Baumann - Folsom CA, US
Ki W. Yoon - Folsom CA, US
Rafi M. Saied - Folsom CA, US
Robert L. Farrell - Gold River CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/38

US Classification:

712221, 712 23

Abstract:

Techniques for control word prediction and speculative execution. In one embodiment, an apparatus includes a control word predictor, execution resources, and a comparison module. The control word predictor of this embodiment predicts a predicted control word for execution of operations in response to a control word changing operation. The execution resources of this embodiment speculatively execute the plurality of operations utilizing the predicted control word, and the comparison module determines if the predicted control word matches an actual control word set by the control word changing operation or a plurality of other control words, and to cause re-execution of said plurality of operations if said actual control word matches any of the plurality of other control words.

US Patent:

8151061, Apr 3, 2012

Filed:

Mar 10, 2009

Appl. No.:

12/401499

Inventors:

Robert L. Farrell - Granite Bay CA, US
Michael J. Muchnick - Fair Oaks CA, US
Altug Koker - El Dorado Hills CA, US
Zeev Offen - Haifa, IL
Ariel Berkovits - Yuvalim, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

711143, 711 1, 711117, 365 491

Abstract:

A platform may comprise a core coherency domain, graphics coherency domain and a non-coherent domain. A graphics acceleration unit (GAU) of the graphics coherency domain may generate data units from an application and the data units may comprise display data units. The GAU may annotate the display data units with an annotation value before flushing the display data units to an on-die cache. The GAU may identify modified display data units among the display data units stored in the on-die cache and issue flush commands to cause flushing of the modified display data units from the on-die cache to a main memory. The display engine of the non-coherent domain may use the modified display data units stored in the main memory to render a display on a display device.

US Patent:

8600359, Dec 3, 2013

Filed:

Sep 10, 2012

Appl. No.:

13/608071

Inventors:

Mark Bailey - Glendora CA, US
James E. Christensen - Cortlandt Manor NY, US
Steven D. Daniels - Merrick NY, US
Jason B. Ellis - New York NY, US
Robert G. Farrell - Cornwall NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04M 3/42

US Classification:

4554141, 455406, 455416, 455417, 37926501, 37926502, 37926503, 37926513, 37926607, 379279

Abstract:

A method for administering a communication session includes initiating a session between a server and a user device, the user device associated with a user phone number, associating the user phone number and a first session state phone number with a state of the session, and sending a first message associated with the state of the session from the server to the user device, the first message sent from the first session state phone number to the user phone number.

US Patent:

8643660, Feb 4, 2014

Filed:

Dec 20, 2012

Appl. No.:

13/722440

Inventors:

Zeev Offen - Folsom CA, US
Ariel Berkovits - Yuvalim, IL
Thomas A. Piazza - Granite Bay CA, US
Robert L. Farrell - Granite Bay CA, US
Altug Koker - El Dorado Hills CA, US
Opher Kahn - Zichron Yacov, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 5/36

US Classification:

345557

Abstract:

A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

US Patent:

20090248983, Oct 1, 2009

Filed:

Mar 28, 2008

Appl. No.:

12/057601

Inventors:

Zeev Offen - Haifa, IL
Ariel Berkovits - Yuvalim, IL
Thomas A. Piazza - Granite Bay CA, US
Robert L. Farrell - Granite Bay CA, US
Altug Koker - El Dorado Hills CA, US
Opher Kahn - Zichron, IL

International Classification:

G06F 12/08

US Classification:

711122, 711E12016

Abstract:

A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

US Patent:

20090322747, Dec 31, 2009

Filed:

Jun 30, 2008

Appl. No.:

12/215920

Inventors:

Robert Farrell - Granite Bay CA, US

International Classification:

G06T 15/40

US Classification:

345422

Abstract:

The rapid depth testing for hidden surface removal in graphics processing may be achieved by depth testing representative pixels of a group of pixels. In one embodiment, the worst case pixels of a group of pixels can be identified. The worst case pixels can then be compared to worst case values stored in a hierarchical Z-buffer. Depending on the results, the entire set of pixels of the group may pass or fail the depth test. As a result, in some cases, it is not necessary to depth test every pixel.

US Patent:

20100031268, Feb 4, 2010

Filed:

Jul 31, 2008

Appl. No.:

12/221083

Inventors:

Michael K. Dwyer - El Dorado Hills CA, US
Robert L. Farrell - Granite Bay CA, US
Hong Jiang - El Dorado Hills CA, US
Thomas A. Piazza - Granite Bay CA, US

International Classification:

G06F 9/46

US Classification:

718106

Abstract:

Techniques are described that can be used to ensure ordered computation and/or retirement of threads in a multithreaded environment. Threads may contain bundled instances of work, each with unique ordering restrictions relative to other instances of work packaged in other threads in the system. When applied to 3D graphics, video and image processing domains allow unrestricted processing of threads until reaching their critical sections. Ordering may be required prior to executing critical sections and beyond.