Robert J Farrell

US Patent:

20140077031, Mar 20, 2014

Filed:

Sep 14, 2012

Appl. No.:

13/620679

Inventors:

Brenda Benedetti - Seattle WA, US
Robert S. Farrell - Seattle WA, US
Luis R. Leon - Federal Way WA, US
Justin H. Lan - Bothell WA, US
Garry A. Booker - Lake Stevens WA, US

Assignee:

THE BOEING COMPANY - Seal Beach CA

International Classification:

B64C 1/40
E04B 1/84
B32B 15/01
B32B 3/28
B32B 3/12

US Classification:

244 1 N, 428603, 428593, 181292, 181296

Abstract:

An acoustic-attenuating wall panel for a nacelle of a turbine engine may include a radiused portion. The radiused portion may include an airflow surface having a concave configuration and which may be exposed to an airflow passing through the nacelle. The radiused portion may include an acoustic attenuating section.

US Patent:

48071099, Feb 21, 1989

Filed:

Jan 14, 1987

Appl. No.:

7/006353

Inventors:

Robert L. Farrell - Portland OR
Alireza Sarabi - Hillsboro OR
Raymond S. Tetrick - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1340

US Classification:

364200

Abstract:

A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting data traffic along the bus. The local bus employs a message control method and apparatus which includes the ability to assert a WAIT signal when the processing resource is replying to a request. By asserting the WAIT signal all other operations on the bus are delayed until the transfer is complete. The use of the WAIT signal enables a device operating at a different speed from the primary processing resource to respond across the bus in a manner that is synchronized to the clock speed of the primary processing resource.

US Patent:

52936031, Mar 8, 1994

Filed:

Jun 4, 1991

Appl. No.:

7/710079

Inventors:

Peter D. MacWilliams - Aloha OR
Clair C. Webb - Aloha OR
Robert L. Farrell - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

395425

Abstract:

An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

US Patent:

53554671, Oct 11, 1994

Filed:

Mar 8, 1994

Appl. No.:

8/208090

Inventors:

Peter D. MacWilliams - Aloha OR
Robert L. Farrell - Portland OR
Adalberto Golbert - Haifa, IL
Itzik Silas - Haifa, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

395425

Abstract:

A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.

US Patent:

45702209, Feb 11, 1986

Filed:

Nov 25, 1983

Appl. No.:

6/555027

Inventors:

Raymond S. Tetrick - Portland OR
John Beaston - Hillsboro OR
Robert L. Farrell - Portland OR
Alireza Sarabi - Hillsboro OR
Sudarshan Balachandran - Aloha OR
Edwin L. Jacks - Beaverton OR
Steven D. Kassel - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1516

US Classification:

364200

Abstract:

A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.

US Patent:

54886392, Jan 30, 1996

Filed:

Dec 21, 1993

Appl. No.:

8/171554

Inventors:

Peter D. MacWilliams - Aloha OR
Dror Avni - Haifa, IL
Avi Liebermensch - Kfar Vradim, IL
Anan Baransy - Nazareth, IL
Robert L. Farrell - Hillsborough NJ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 700

US Classification:

375355

Abstract:

A method and apparatus for synchronizing an asynchronous signal to a clock signal. The apparatus includes an enable generator, first, second and third sampling circuits, a selecting circuit, and can include a latching circuit. The enable generator is coupled to the first sampling circuit by a first enable line, to the second sampling circuit by a second enable line, and to the third sampling circuit by a third enable line. The first, second, and third sampling circuits are coupled to receive the asynchronous signal. The selecting circuit is coupled to receive the output signals of the first, second and third sampling circuits. For the first sampling circuit, the following steps are performed: sampling the asynchronous signal, generating an output signal for the sampling circuit, waiting a period of time, and selecting the sampling circuit's output signal. These steps are also performed for the second sampling circuit and the third sampling circuit.

US Patent:

52281345, Jul 13, 1993

Filed:

Jun 4, 1991

Appl. No.:

7/710075

Inventors:

Peter D. MacWilliams - Aloha OR
Clair C. Webb - Aloha OR
Robert L. Farrell - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208
G06F 1228

US Classification:

395425

Abstract:

An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cache line to be read/written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

US Patent:

20210025828, Jan 28, 2021

Filed:

Oct 14, 2020

Appl. No.:

17/070868

Inventors:

- Westbrook ME, US
Robert P. Farrell - Gray ME, US

International Classification:

G01N 21/78
G01N 33/487
G01N 33/543
G01N 33/558
G08B 5/36

Abstract:

An instrument for reading a lateral flow assay device by detecting color changes based on human perception includes an optics module having a camera, a signal processor, a storage memory and a comparator circuit. The storage memory has stored therein a dataset of sample readings of reference assay devices similar in structure and function to that of the lateral flow assay device. The sample readings are based on human visual perceptions of colorimetric changes in the detection zones of the reference assay devices. The comparator circuit compares the measured colorimetric data relating to the assay device read by the instrument with the stored database of sample readings based on human visual perceptions of the colorimetric changes of the reference assay devices, and generates a comparison signal which is provided to the signal processor. The signal processor generates a determination signal indicative of the presence, absence or quantity of an analyte.