Robert S Farrell

US Patent:

6381704, Apr 30, 2002

Filed:

Jan 29, 1999

Appl. No.:

09/240271

Inventors:

Francisco A. Cano - Missouri City TX
Rajib Nag - Missouri City TX
Robert E. Farrell - Murphy TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 104

US Classification:

713600, 713400, 713500, 710 58, 714731

Abstract:

A clock generation circuit with a selectable non-overlap time period is described for use on an integrated circuit. A master clock signal M which has a latching edge is formed in response to a reference clock signal fclk. A slave clock signal S which has a driving edge is also formed in response to the reference clock signal. The driving edge of slave clock S is delayed by a non-overlap feedback path so that the driving edge is delayed by the non-overlap time period after the latching edge of master clock M. The value of the non-overlap time period is selected by switching delay circuitry in or out of the non-overlap feedback path on signal line. A control signal STRSTST is set high or low to select the value of the non-overlap time period. A sense circuit or a scan latch also can select the non-overlap time period.