Robert L Farrell

US Patent:

42821762, Aug 4, 1981

Filed:

Sep 24, 1979

Appl. No.:

6/078560

Inventors:

Robert E. Farrell - Springfield MA

Assignee:

Package Machinery Company - East Longmeadow MA

International Classification:

B29F 106

US Classification:

26432813

Abstract:

An injection molding machine having a ram for injecting a settable material into an associated mold includes a hydraulic actuator formed by a piston and cylinder assembly which displaces the ram during the injection operation. The piston is an unbalanced area piston which permits the ram to be displaced in both a regenerative and a nonregenerative feed mode. Fluid controls for operating the piston and cylinder assembly include a regeneration valve in fluid communication through the cylinder with opposite sides of the unbalanced piston to permit regenerative feed of the piston and ram in one valve position or to permit nonregenerative feed in another valve position. Displacing the ram in the regenerative or nonregenerative modes of operation allows the mold to be filled at different rates or pressures.

US Patent:

40884325, May 9, 1978

Filed:

Mar 1, 1977

Appl. No.:

5/773300

Inventors:

Robert E. Farrell - Springfield MA

Assignee:

Package Machinery Company - East Longmeadow MA

International Classification:

B29F 100
B30B 116
B29C 306

US Classification:

4254516

Abstract:

An injection molding machine has two stationary platens interconnected by tie bars and an immediate third platen which is movable on the tie bars. Separable mold portions are mounted respectively on one of the stationary platens and the third platen so that reciprocating movement of the third platen along the tie bars opens and closes the mold portions. A pair of toggle linkage mechanisms positioned at opposite sides of the machine and connecting with the movable third platen and one of the other platens are used to lockup the mold portions when the linkages assume their toggle positions. To move the toggle mechanisms into the toggle positions, a crosshead on slide rods connects with the mechanisms and is pushed away from the third platen at lockup by two piston and cylinder assemblies extending between the platen and the crosshead. The positioning of the cylinders and crosshead minimizes the overall length of the molding machine and permits mold lockup to be triggered more accurately.

US Patent:

43011004, Nov 17, 1981

Filed:

May 23, 1980

Appl. No.:

6/152616

Inventors:

Robert E. Farrell - Springfield MA

Assignee:

Package Machinery Company - East Longmeadow MA

International Classification:

B29F 106

US Classification:

264 405

Abstract:

The clamping preload in a molding machine or the like is set by adjusting the length of tie bars which support two die plates for opening and closing movement and a thrust plate. A clamping mechanism of given stroke is positioned between the thrust plate and one of the disc plates, and operates to close the die plates at one limit of the clamping stroke. With the clamping mechanism set at its limit and the tie bars set to establish a slight spacing between the die plates, the length of the tie bars is adjusted by means of a drive motor until the die plates are in contact without substantial preload. The clamping mechanism then opens the die plates and the drive motor is further energized to adjust the length of the tie bars and bring the die plates closer to one another by an amount corresponding to a preselected preload. The adjustment is measured from a high ratio mechanical drive connecting the drive motor to the adjustable tie bars, and the measured adjustment is compared with a desired adjustment corresponding to the preselected preload to deenergize the drive motor when the desired adjustment is reached.

US Patent:

48071099, Feb 21, 1989

Filed:

Jan 14, 1987

Appl. No.:

7/006353

Inventors:

Robert L. Farrell - Portland OR
Alireza Sarabi - Hillsboro OR
Raymond S. Tetrick - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1340

US Classification:

364200

Abstract:

A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting data traffic along the bus. The local bus employs a message control method and apparatus which includes the ability to assert a WAIT signal when the processing resource is replying to a request. By asserting the WAIT signal all other operations on the bus are delayed until the transfer is complete. The use of the WAIT signal enables a device operating at a different speed from the primary processing resource to respond across the bus in a manner that is synchronized to the clock speed of the primary processing resource.

US Patent:

42564476, Mar 17, 1981

Filed:

Oct 2, 1978

Appl. No.:

5/948082

Inventors:

Robert E. Farrell - Springfield MA

Assignee:

Package Machinery Company - East Longmeadow MA

International Classification:

B29F 104
B29F 106

US Classification:

425159

Abstract:

An injection molding machine having a ram for injecting a settable material into an associated mold includes a hydraulic actuator formed by a piston and cylinder assembly which displaces the ram during the injection operation. The piston is an unbalanced area piston which permits the ram to be displaced in both a regenerative and a nonregenerative feed mode. Fluid controls for operating the piston and cylinder assembly include a regeneration valve in fluid communication through the cylinder with opposite sides of the unbalanced piston to permit regenerative feed of the piston and ram in one valve position or to permit nonregenerative feed in another valve position. Displacing the ram in the regenerative or nonregenerative modes of operation allows the mold to be filled at different rates or pressures.

US Patent:

52936031, Mar 8, 1994

Filed:

Jun 4, 1991

Appl. No.:

7/710079

Inventors:

Peter D. MacWilliams - Aloha OR
Clair C. Webb - Aloha OR
Robert L. Farrell - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

395425

Abstract:

An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

US Patent:

53554671, Oct 11, 1994

Filed:

Mar 8, 1994

Appl. No.:

8/208090

Inventors:

Peter D. MacWilliams - Aloha OR
Robert L. Farrell - Portland OR
Adalberto Golbert - Haifa, IL
Itzik Silas - Haifa, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

395425

Abstract:

A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.

US Patent:

45702209, Feb 11, 1986

Filed:

Nov 25, 1983

Appl. No.:

6/555027

Inventors:

Raymond S. Tetrick - Portland OR
John Beaston - Hillsboro OR
Robert L. Farrell - Portland OR
Alireza Sarabi - Hillsboro OR
Sudarshan Balachandran - Aloha OR
Edwin L. Jacks - Beaverton OR
Steven D. Kassel - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1516

US Classification:

364200

Abstract:

A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.