Robert A Flanagan

US Patent:

6594476, Jul 15, 2003

Filed:

Aug 2, 2000

Appl. No.:

09/631015

Inventors:

Robert C. Flanagan - Thousand Oaks CA
Mark B. Bahu - Ventura CA

Assignee:

American Nucleonics Corporation - Westlake Village CA

International Classification:

H04B 106

US Classification:

4552781, 455296

Abstract:

In accordance with one form of the present invention, an Adaptively Peaked Super-Regenerative Filter (APSRF) is provided, which preferably includes an interference suppression system (ISS), a summing block, a phase splitter, one or more variable attenuators, three couplers, an amplifier and a filter. The APSRF provides for significant narrowing of the bandwidth and a significant increase in the SNR and Q transfer function of the filter. The output of the amplifier or filter is sampled by one of the couplers and used as a reference sample signal to the ISS. The ISS includes an adaptive loop, which adjusts the reference sample signal in phase and amplitude to form a replica signal. The replica signal is designed to cancel an input sample signal taken from another coupler and applied to the summing block. An output of the summing block provides an error sample signal to the ISS, which enables the ISS to adaptively optimize the nulling function by adjusting the amplitude and phase of the replica signal. The phase splitter provides a copy of the replica signal having a 180-degree phase shift.

US Patent:

40073319, Feb 8, 1977

Filed:

Aug 13, 1975

Appl. No.:

5/604121

Inventors:

Robert C. Flanagan - Westlake Village CA

Assignee:

Bunker Ramo Corporation - Oak Brook IL

International Classification:

H04L 1524

US Classification:

178 88

Abstract:

A digital system is disclosed for demodulating relative phase-shift modulated binary data using a delay circuit to store one data bit period of sample bits for phase comparison with the next data bit period of sample bits, and a cascaded delay circuit of the same length to effectively repeat the demodulation one data bit period later. An up-down counter effectively integrates the difference between current demodulated sample bits and the demodulated sample bits of the previous data bit period to enhance data bit detection. Such data demodulation is used from a selected one of three channels, a center channel for no Doppler shift compensation, and two channels for positive and negative Doppler shift compensation. All delay circuits are implemented with random access memory units, and all units in each channel are addressed by a single counter preset each time it overflows in response to counting clock pulses to set the length of the delay circuits according to the average of any expansion or contraction of a data bit period expected due to Doppler shift.