Robert C Flores

US Patent:

8527080, Sep 3, 2013

Filed:

Oct 2, 2008

Appl. No.:

12/244735

Inventors:

Shay Assaf - Cupertino CA, US
Venkatesh Babu - San Jose CA, US
Robert D. Flores - Campbell CA, US
Brendan Hickey - San Francisco CA, US
Krishna Kuttannair - San Jose CA, US
Song J. Park - Pleasanton CA, US
Adrian Rhee - Santa Clara CA, US
Chongyang Chris Wang - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 19/00

US Classification:

700101, 700121, 718104

Abstract:

A method and system for managing process jobs in a semiconductor fabrication facility is described. In one embodiment, the method includes receiving a plurality of process jobs associated with one or more priorities. The method further includes executing the plurality of process jobs in an order reflecting the priorities. The order is modifiable in real time upon receiving a new process job with a priority higher than the priorities of the plurality of process jobs.

US Patent:

57468842, May 5, 1998

Filed:

Aug 13, 1996

Appl. No.:

8/696774

Inventors:

Subhash Gupta - Saratoga CA
Robert Flores - Austin TX
Michael Ross Stamm - Austin TX
Eric Thomas Sharp - Austin TX
Erich W. E. Denninger - Buda TX
Pamela G. Dye - Austin TX
Joel Samuel Utz - Austin TX
James K. Kai - San Francisco CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2100

US Classification:

1566431

Abstract:

A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50. degree. The first stage of the fluted via extends a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via.

US Patent:

58411968, Nov 24, 1998

Filed:

Nov 14, 1997

Appl. No.:

8/970314

Inventors:

Subhash Gupta - Saratoga CA
Robert Flores - Austin TX
Michael Ross Stamm - Austin TX
Eric Thomas Sharp - Austin TX
Erich W. E. Denninger - Buda TX
Pamela G. Dye - Austin TX
Joel Samuel Utz - Austin TX
James K. Kai - San Francisco CA

Assignee:

Advanced Micro Devices, Inc.

International Classification:

H01L 2100

US Classification:

257774

Abstract:

A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50. degree. The first stage of the fluted via exterds a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via.