James Y. Hurt - San Diego CA, US Michael A. Howard - San Diego CA, US Robert J. Fuchs - San Diego CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
H03M013/27 H03M013/29
US Classification:
714701, 714702, 714755
Abstract:
A method and apparatus for encoding multiple bits in parallel wherein outputs are generated recursively. During each clock cycle, the encoder processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units, which are then each uniquely addressed to provide data to parallel encoders.
Method And Apparatus For Efficient Use Of Communication Resources In A Communication System
Quaeed Motiwala - San Diego CA, US Christopher C. Riddle - San Diego CA, US Luca Blessent - San Diego CA, US Shih-Yi Yeh - Santee CA, US Robert J. Fuchs - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H04B 1/00
US Classification:
375142, 375143, 375150, 375152, 375326
Abstract:
The frame of data is partitioned into a plurality of portions of data symbols. A plurality of channel elements is assigned to demodulate data symbols of correspondingly the plurality of portions of data symbols. The number of the plurality of portions of data symbols is higher in a case at high data rate than a case at low data rate.
Peter Gaal - San Diego CA, US Robert J. Fuchs - San Diego CA, US Yongbin Wei - San Diego CA, US Ke Liu - San Diego CA, US Hanfang Pan - San Diego CA, US Durga Prasad Malladi - San Diego CA, US Daniel T. Macek - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H04J 11/00 H04W 4/00
US Classification:
370206, 370208, 370329
Abstract:
Efficient apparatus and method for Zadoff-Chu (“Chu”) sequence generation avoids additional processing and hardware complexity of conventional quadratic generating formula followed by Discrete Fourier Transform (DFT) with a reference signal generator that produces both a Zadoff-Chu sequence and its DFT. In the wireless communication system (e. g. , Long Term Evolution (LTE) system), Chu sequences are extensively used, especially in the uplink (UL). Because of the single carrier operating mode, transmitting a Chu sequence in principle involves a succession of generating that sequence, performing a DFT operation and then an IFFT operation. Assuming that the sequence length is N, the initial sequence generation requires 2N multiplications and the DFT requires more than N log 2(N) multiplications. Given the frequent processing of Chu sequences, this would represent a complexity burden. The invention makes it possible to perform the sequence generation and DFT steps without any multiplication operation, except for possibly calculating certain initial parameters.
An embodiment of the present invention pertains to an apparatus and method for caching pixel data used in filtering edges of video macroblocks. Pixel data which are required to edge filter subsequent macroblocks are temporarily stored in a cache memory. When a macroblock is subsequently being processed, this cached pixel data is read out and used to filter the corresponding edge(s). By caching select pixel values rather than writing them to external memory, the number of memory accesses is dramatically reduced.
Facilitating Noise Estimation In Wireless Communication
Xiaoxia Zhang - San Diego CA, US Darshan Jetly - San Diego CA, US Hao Xu - San Diego CA, US Robert J. Fuchs - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H04W 72/04
US Classification:
370330
Abstract:
Providing for noise estimation in wireless communication, and particularly for access request signals transmitted by a user equipment (UE), is described herein. By way of example, a wireless signal receiver can employ unused signal dimensions of a wireless network for noise estimation. In addition, the unused signal dimensions can be selected for time-frequency resources that are associated with a particular wireless channel, in order to obtain a noise estimate for that channel. By employing unused signal dimensions, a noise measurement is likely to include no other signal transmissions, and provide an accurate estimate of noise on that channel. According to various aspects of the subject disclosure, one or more Chu sequences employed for signal transmissions, root sequences thereof, or one or more cyclic shifts of a root sequence can be employed for the unused signal dimension.
Optimizing A Receiver For Multiple Antenna Configurations
Hao Xu - San Diego CA, US Robert Jason Fuchs - San Diego CA, US Ke Liu - San Diego CA, US James Corona - San Diego CA, US Zhifei Fan - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H04L 27/06
US Classification:
375340
Abstract:
A method for optimizing a multiple input multiple output (MIMO) receiver for multiple antenna configurations is disclosed. A noise covariance is determined based on a noise estimate of a wireless signal. A Cholesky decomposition matrix is determined based on the noise covariance. A whitening matrix is determined based on the Cholesky decomposition matrix. The wireless signal is whitened using the whitening matrix.
Software Management With Hardware Traversal Of Fragmented Llr Memory
Robert Jason Fuchs - San Diego CA, US Michael A. Kongelf - San Diego CA, US Christian O. Thelen - San Diego CA, US Rajat R. Dhawan - San Diego CA, US Hao Xu - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G06F 12/00 G06F 12/02
US Classification:
711103, 711154, 711E12002, 711E12008
Abstract:
Certain aspects of the present disclosure relate to a method and apparatus for processing wireless communications. According to certain aspects, a linked list of chunks of memory used to store logarithmic likelihood ratio (LLR) values for a transport block is generated. Each chunk holds LLR values for a code block of the transport block. The linked list is then provided to a hardware circuit for traversal. According to certain aspects, the hardware circuit may be an application specific integrated circuit (ASIC) processor or field programmable gate array (FPGA) configured to traverse the linked list of chunks of memory used to store LLR values.
Hardware Implementation Of Uplink Receiver With Matched Throughput
Robert Jason Fuchs - San Diego CA, US Devyani N. Pisolkar - San Diego CA, US Hao Xu - San Diego CA, US Xiaoxia Zhang - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H04W 72/04
US Classification:
370329
Abstract:
Certain aspects of the present disclosure provide an apparatus and techniques for efficiently processing uplink communications. A telecommunications receiver processor architecture is provided that may be utilized with a LTE eNodeB base station wherein the data path throughput is optimally matched for a Physical Uplink Shared Channel (PUSCH) receiver. According to certain aspects, the receiver may be configured to perform operations on OFDMs symbols in an interleaved order. Additionally, the receiver may instantiate multiple IDFT engines to process multiple OFDM symbols in parallel.
Gold Und Vergoldung Bei Plinius Dem Alteren: Gold Und Vergoldung in Der Naturalis Historia Des Alteren Plinius Und Anderen Antiken Texten Mit Exkursen Zu Verschiedenen Einzelfragen Naturalis Historia
Greatcall Nov 2016 - Nov 2017
Automation Engineer
Greatcall Nov 2016 - Nov 2017
Software Engineer
Greatcall May 1, 2015 - Nov 2016
Sqa
Sony Electronics Jul 2012 - May 2015
Quality Assurance Engineer
Dynalectric San Diego Jun 2010 - Sep 2010
Professional Engineering Intern
Education:
California Polytechnic State University - San Luis Obispo 2006 - 2011
Bachelors, Bachelor of Science, Electronics Engineering
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