Robert John Gauthier

US Patent:

6411480, Jun 25, 2002

Filed:

Mar 1, 1999

Appl. No.:

09/259541

Inventors:

Robert J. Gauthier - Hinesburg VT
Steven H. Voldman - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 900

US Classification:

361 56

Abstract:

An ESD protection circuit which may be implemented in thin epitaxial substrate surfaces. The protection device includes a MOSFET transistor or bipolar transistor implemented in a trench isolated area of the substrate. The isolation of the MOSFET transistor permits the substrate region to be pumped with an electric charge which reduces the trigger/snapback voltage and MOSFET threshold voltage for the device. A trigger current supplies the pumping current to the isolated substrate area when a transient voltage is applied thus lowering the trigger/snapback voltage of the MOSFET transistor in the presence of a transient voltage.

US Patent:

6838323, Jan 4, 2005

Filed:

Jan 13, 2003

Appl. No.:

10/341182

Inventors:

Robert J. Gauthier - Hinesburg VT, US
Edward J. Nowak - Essex Junction VT, US
Xiaowei Tian - Essex Junction VT, US
Minh H. Tong - Essex Junction VT, US
Steven H. Voldman - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100
H01L 2362

US Classification:

438155, 438179, 257355, 257358, 257363

Abstract:

A structure and process for making a non-aligned MOSFET structure for ESD protection using resistor wells as the diffusions and adjustable capacitors. The present invention compensates the shallow extension region without the need for additional masks. The source/drain doping is less than that of a normal MOSFET but extends deeper into the silicon since the present invention uses a resistor well as the source/drain. The deeper emitter/collector increases the second trigger current of the NFET when used as an ESD protection device.

US Patent:

7098513, Aug 29, 2006

Filed:

Jan 17, 2005

Appl. No.:

10/905682

Inventors:

Kiran V. Chatty - Williston VT, US
Robert J. Gauthier - Hinesburg VT, US
Terence B. Hook - Jericho VT, US
Christopher S. Putnam - Hinesburg VT, US
Mujahid Muhammad - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76

US Classification:

257382, 257119, 257379

Abstract:

A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.

US Patent:

7645676, Jan 12, 2010

Filed:

Oct 29, 2007

Appl. No.:

11/927135

Inventors:

Toshiharu Furukawa - Essex Junction VT, US
Robert J. Gauthier - Hinesburg VT, US
David Vaclav Horak - Essex Junction VT, US
Jack Allan Mandelman - Flat Rock NC, US
William Robert Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/76

US Classification:

438407, 438221, 438296, 438423, 438520, 438766, 257E21546, 257E21551

Abstract:

Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.

US Patent:

7700428, Apr 20, 2010

Filed:

May 9, 2008

Appl. No.:

12/117950

Inventors:

Wagdi W. Abadeer - Jericho VT, US
Kiran V. Chatty - Williston VT, US
Robert J. Gauthier - Hinesburg VT, US
Jed H. Rankin - Richmond VT, US
Yun Shi - South Burlington VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8238

US Classification:

438211, 257E21422, 257E21638

Abstract:

Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body.

US Patent:

7709896, May 4, 2010

Filed:

Mar 8, 2006

Appl. No.:

11/370369

Inventors:

Cornelius Christian Russ - Diedorf, DE
David Alvarez - Essex VT, US
Kiran V. Chatty - Williston VT, US
Jens Schneider - Munich, DE
Robert Gauthier - Hinesburg VT, US
Martin Wendel - Hohenbrunn, DE

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 23/62

US Classification:

257355, 257357, 257362, 257E2706, 257E29255

Abstract:

An ESD protection device includes a source region, a channel region adjacent the source region, and an elongated drain region spaced from the source region by the channel region. The elongated drain region includes an unsilicided portion adjacent the channel and a silicided portion spaced from channel region by the unsilicided portion. A first ESD region is located beneath the silicided portion of the elongated drain region and a second ESD region is located beneath the unsilicided portion of the elongated drain region, the second ESD region being spaced from the first ESD region.

US Patent:

7709926, May 4, 2010

Filed:

Apr 24, 2008

Appl. No.:

12/108924

Inventors:

Wagdi W. Abadeer - Jericho VT, US
Kiran V. Chatty - Williston VT, US
Robert J. Gauthier - Hinesburg VT, US
Jed H. Rankin - Richmond VT, US
Robert R. Robison - Colchester VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/06

US Classification:

257510, 257506, 257509, 257513, 257E29019, 257E2902

Abstract:

Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.

US Patent:

7714356, May 11, 2010

Filed:

Oct 31, 2007

Appl. No.:

11/931517

Inventors:

Michel J. Abou-Khalil - Essex Junction VT, US
Robert Gauthier - Hinesburg VT, US
Hongmei Li - Williston VT, US
Junjun Li - Williston VT, US
Souvick Mitra - Burlington VT, US
Christopher S. Putnam - Hinesburg VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/06

US Classification:

257173, 257213, 257362, 257E27016

Abstract:

A design structure for a circuit providing the same trigger voltage across the multiple fingers is provided, which comprises a data representing an external current injection source connected to individual fingers of a multi-finger semiconductor device. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source is adjusted so that each finger has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.