Robert A Gauthier

US Patent:

6411480, Jun 25, 2002

Filed:

Mar 1, 1999

Appl. No.:

09/259541

Inventors:

Robert J. Gauthier - Hinesburg VT
Steven H. Voldman - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 900

US Classification:

361 56

Abstract:

An ESD protection circuit which may be implemented in thin epitaxial substrate surfaces. The protection device includes a MOSFET transistor or bipolar transistor implemented in a trench isolated area of the substrate. The isolation of the MOSFET transistor permits the substrate region to be pumped with an electric charge which reduces the trigger/snapback voltage and MOSFET threshold voltage for the device. A trigger current supplies the pumping current to the isolated substrate area when a transient voltage is applied thus lowering the trigger/snapback voltage of the MOSFET transistor in the presence of a transient voltage.

US Patent:

6838323, Jan 4, 2005

Filed:

Jan 13, 2003

Appl. No.:

10/341182

Inventors:

Robert J. Gauthier - Hinesburg VT, US
Edward J. Nowak - Essex Junction VT, US
Xiaowei Tian - Essex Junction VT, US
Minh H. Tong - Essex Junction VT, US
Steven H. Voldman - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100
H01L 2362

US Classification:

438155, 438179, 257355, 257358, 257363

Abstract:

A structure and process for making a non-aligned MOSFET structure for ESD protection using resistor wells as the diffusions and adjustable capacitors. The present invention compensates the shallow extension region without the need for additional masks. The source/drain doping is less than that of a normal MOSFET but extends deeper into the silicon since the present invention uses a resistor well as the source/drain. The deeper emitter/collector increases the second trigger current of the NFET when used as an ESD protection device.

US Patent:

7098513, Aug 29, 2006

Filed:

Jan 17, 2005

Appl. No.:

10/905682

Inventors:

Kiran V. Chatty - Williston VT, US
Robert J. Gauthier - Hinesburg VT, US
Terence B. Hook - Jericho VT, US
Christopher S. Putnam - Hinesburg VT, US
Mujahid Muhammad - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76

US Classification:

257382, 257119, 257379

Abstract:

A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.

US Patent:

7700428, Apr 20, 2010

Filed:

May 9, 2008

Appl. No.:

12/117950

Inventors:

Wagdi W. Abadeer - Jericho VT, US
Kiran V. Chatty - Williston VT, US
Robert J. Gauthier - Hinesburg VT, US
Jed H. Rankin - Richmond VT, US
Yun Shi - South Burlington VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8238

US Classification:

438211, 257E21422, 257E21638

Abstract:

Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body.

US Patent:

7709926, May 4, 2010

Filed:

Apr 24, 2008

Appl. No.:

12/108924

Inventors:

Wagdi W. Abadeer - Jericho VT, US
Kiran V. Chatty - Williston VT, US
Robert J. Gauthier - Hinesburg VT, US
Jed H. Rankin - Richmond VT, US
Robert R. Robison - Colchester VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/06

US Classification:

257510, 257506, 257509, 257513, 257E29019, 257E2902

Abstract:

Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.

US Patent:

8637388, Jan 28, 2014

Filed:

Jan 16, 2013

Appl. No.:

13/742508

Inventors:

Robert J. Gauthier - Hinesburg VT, US
Tom C. Lee - Essex Junction VT, US
Junjun Li - Williston VT, US
Souvick Mitra - Burlington VT, US
Christopher S. Putnam - Hinesburg VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/768

US Classification:

438584

Abstract:

A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.

US Patent:

20010029084, Oct 11, 2001

Filed:

May 23, 2001

Appl. No.:

09/862451

Inventors:

Robert Gauthier - Hinesburg VT, US
Dominic Schepis - Wappingers Falls NY, US
William Tonti - Essex Junction VT, US
Steven Voldman - South Burlington VT, US

International Classification:

H01L021/76
H01L023/48

US Classification:

438/430000, 257/750000

Abstract:

Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.

US Patent:

20010031552, Oct 18, 2001

Filed:

Mar 16, 2001

Appl. No.:

09/809014

Inventors:

Robert Gauthier - Hinesburg VT, US
Randy Mann - Jericho VT, US
Steven Voldman - South Burlington VT, US

International Classification:

H01L021/44

US Classification:

438/655000

Abstract:

The current density profile in the conduction channel of a field effect transistor is controlled and thermal gradients are limited under extreme operating conditions by providing lateral resistive ballasting at the source/drain regions adjacent the conduction channel. A distributed resistance is formed by inhibiting conversion of a region of deposited salicide from a high resistance phase state to a low resistance phase state through formation of the deposit with a width or area less than a critical dimension.