Robert S Greenberg

US Patent:

6339434, Jan 15, 2002

Filed:

Nov 23, 1998

Appl. No.:

09/198314

Inventors:

Michael G. West - Portland OR
Robert Y. Greenberg - Portland OR
Alan L. Zimmerman - Portland OR

Assignee:

Pixelworks - Tualatin OR

International Classification:

G09G 500

US Classification:

345667, 348581

Abstract:

An image scaling circuit for increasing or decreasing the size of a sampled image to match a fixed resolution display. The circuit includes means for resizing the image in the horizontal and vertical dimension using independent sample rate converters. The sample rate converters increase or decrease the image size by a factor of Lx/Mx in the horizontal dimension and Ly/My in the vertical dimension where Lx and Ly are integers and Mx and My are decimal numbers of arbitrary precision to provide fine scaling control. In addition, image warping is conveniently implemented by varying the down sample ratios Mx and My on a pixel by pixel and/or line by line basis.

US Patent:

6611260, Aug 26, 2003

Filed:

May 17, 1999

Appl. No.:

09/313060

Inventors:

Robert Y. Greenberg - Portland OR
Michael G. West - Portland OR

Assignee:

Pixelworks, Inc - Tualatin OR

International Classification:

G09G 500

US Classification:

345204, 345212, 345213

Abstract:

The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers.

US Patent:

6903733, Jun 7, 2005

Filed:

Apr 1, 2003

Appl. No.:

10/405775

Inventors:

Robert Y. Greenberg - Portland OR, US
Michael G. West - Portland OR, US

Assignee:

Pixelworks, Inc. - Tualatin OR

International Classification:

G09G005/00

US Classification:

345204, 345212, 345213

Abstract:

The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers.

US Patent:

7002564, Feb 21, 2006

Filed:

Mar 6, 2002

Appl. No.:

10/092180

Inventors:

Robert Y. Greenberg - Portland OR, US

Assignee:

Pixelworks, Inc. - Tualatin OR

International Classification:

G09G 5/00

US Classification:

345204, 345 89, 348443

Abstract:

The invention describes a system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input vertical refresh rate and displays the image data at a vertical refresh rate that is a predetermined fraction of the input vertical refresh rate.

US Patent:

7170323, Jan 30, 2007

Filed:

May 9, 2005

Appl. No.:

11/125933

Inventors:

Robert Greenberg - Portland OR, US

Assignee:

Pixelworks, Inc. - Tualatin OR

International Classification:

H03L 7/06

US Classification:

327158, 327150

Abstract:

We describe and claim a delay locked loop harmonic detector and associated method. A delay locked loop includes a detection circuit to generate a detection signal responsive to an input clock and a control circuit to synchronize the delay locked loop to a fundamental of the input clock responsive to the detection signal. A method includes detecting harmonic synchronization in a delay locked loop responsive to an input clock and locking the delay locked loop to a fundamental of the input clock responsive to the detecting.

US Patent:

7217796, May 15, 2007

Filed:

May 22, 2003

Appl. No.:

10/443466

Inventors:

Yan Wang - Scotch Plains NJ, US
Robert Greenberg - Sparta NJ, US
Leonard Presta - San Francisco CA, US
Jonathan A. Pachter - Maplewood NJ, US
Judith Hailey - Edison NJ, US
Peter Brams - Sacramento CA, US
Denise Williams - San Jose CA, US
Mohan Srinivasan - Cupertino CA, US
Diane Feingersh - Union City CA, US

Assignee:

Schering Corporation - Kenilworth NJ

International Classification:

A61K 39/395

US Classification:

5303873, 530350, 530380, 530385, 5303871, 5303877, 5303881, 53038815, 53038824, 4241341, 4241351, 4241411, 4241421, 4241551, 4241741, 435 79, 435188, 4353201

Abstract:

The present invention includes fully human, neutralizing, monoclonal antibodies against human Insulin-like Growth Factor Receptor-I (IGFR1). The antibodies are useful for treating or preventing cancer in a subject. Also included are methods of using and producing the antibodies of the invention.

US Patent:

7327400, Feb 5, 2008

Filed:

Jun 21, 2001

Appl. No.:

09/888271

Inventors:

Robert Y. Greenberg - Portland OR, US

Assignee:

Pixelworks, Inc. - Tualatin OR

International Classification:

H03L 7/00

US Classification:

348536, 348537, 348541

Abstract:

The invention is a circuit and method for automatically adjusting the phase and frequency of a pixel clock derived from analog image data. The circuit includes a phase locked loop circuit adapted to generate a phase locked loop clock responsive to a reference signal and an edge detector circuit adapted to generate an edge pulse signal corresponding to a transition of an analog data signal. A phase detector circuit is adapted to identify a phase of the phase locked loop clock associated to the transition of the analog data and thereby generate a phase adjust signal. A phase adjust circuit is adapted to generate a pixel clock by adjusting the phase of the phase locked loop clock responsive to the phase adjust signal.

US Patent:

7480012, Jan 20, 2009

Filed:

Feb 24, 2005

Appl. No.:

11/066711

Inventors:

Robert Y. Greenberg - Portland OR, US

Assignee:

Pixelworks, Inc. - Tualatin OR

International Classification:

H04N 5/268

US Classification:

348572, 348705

Abstract:

The invention relates to a multiplexed video digitization system and method. The system includes a plurality of analog video signals, a multiplexer to select one of the plurality of analog video signals, and an analog-to-digital converter to convert the selected analog video signal into a digital video signal. The plurality of analog video signals may include component video signals, red, green, and blue signals, or s-video signals. The multiplexer may include control logic to select the one of the plurality of analog video signals. The system may include a plurality of sample and hold circuits to insure time aligned sampling of the corresponding plurality of video signals.

Address:

61 Codding Rd, Norton, MA 02766

Phone:

5086671843

VIN:

JTDKN3DU9A0133222

Make:

TOYOTA

Model:

PRIUS

Year:

2010