Robert G Hartmann

Address:

940 Stone Crk Ct, Longwood, FL 32779

VIN:

1FTKR1EE7APA22725

Make:

FORD

Model:

RANGER

Year:

2010

US Patent:

20130234344, Sep 12, 2013

Filed:

Mar 6, 2012

Appl. No.:

13/413595

Inventors:

Frank J. Juskey - Apopka FL, US
Robert C. Hartmann - Apopka FL, US
Paul D. Bantz - Los Altos CA, US

Assignee:

TRIQUINT SEMICONDUCTOR, INC. - Hillsboro OR

International Classification:

H01L 23/48
H01L 21/50

US Classification:

257778, 438108, 257E2301, 257E21499

Abstract:

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

US Patent:

20190229087, Jul 25, 2019

Filed:

Apr 5, 2019

Appl. No.:

16/376619

Inventors:

- Greensboro NC, US
Robert Hartmann - Apopka FL, US

International Classification:

H01L 23/00
H01L 23/31
H01L 23/498

Abstract:

The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish.

US Patent:

20170047232, Feb 16, 2017

Filed:

Aug 15, 2016

Appl. No.:

15/236586

Inventors:

- Greensboro NC, US
Frank Juskey - Apopka FL, US
Thomas Scott Morris - Lewisville NC, US
Charles E. Carpenter - Orlando FL, US
Robert Hartmann - Apopka FL, US

International Classification:

H01L 21/56
H01L 23/29
H01L 23/31
H01L 25/065
H01L 25/00

Abstract:

The present disclosure relates to a packaging process using a low pressure encapsulant. According to an exemplary process, an assembly including a substrate, a surface mounted device (SMD) mounted on the substrate, and a space between the SMD and the substrate is provided. The SMD has a sealed cavity biased towards the substrate. A sheet mold compound is laid over the SMD and the assembly is heated such that the sheet mold compound transitions to a liquid phase to form a molten mold compound. Next, the assembly is subjected to a vacuum that creates a negative atmosphere allowing the molten mold compound to flow towards the top surface of the substrate and about the SMD. The molten mold compound is then pressed towards the substrate at a low pressure (

US Patent:

20170040273, Feb 9, 2017

Filed:

Aug 1, 2016

Appl. No.:

15/224977

Inventors:

- Greensboro NC, US
Robert Hartmann - Apopka FL, US

International Classification:

H01L 23/00
H01L 23/31
H01L 23/498

Abstract:

The present disclosure relates to a semiconductor package having a substrate structure with selective surface finishes, and a process for making the same. The disclosed semiconductor package includes a substrate body, a first metal structure having a first finish area and a second finish area, a second metal structure having a third finish area, a surface finish, and a tuning wire. The first metal structure and the second metal structure are formed over the substrate body. The surface finish is provided over the first finish area of the first metal structure and at least a portion of the third finish area of the second metal structure. The surface finish is not provided over the second finish area of the first metal structure. The tuning wire is coupled between the first finish area and at least one portion of the third finish area.

US Patent:

20170040276, Feb 9, 2017

Filed:

Aug 1, 2016

Appl. No.:

15/225389

Inventors:

- Greensboro NC, US
Robert Hartmann - Apopka FL, US

International Classification:

H01L 23/00

Abstract:

The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish.

US Patent:

20140106511, Apr 17, 2014

Filed:

Dec 16, 2013

Appl. No.:

14/108093

Inventors:

- Hillsboro OR, US
Robert C. Hartmann - Apopka FL, US
Paul D. Bantz - Los Altos CA, US

Assignee:

TriQuint Semiconductor, Inc. - Hillsboro OR

International Classification:

H01L 23/00

US Classification:

438126

Abstract:

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.