Robert W Hay

US Patent:

6336182, Jan 1, 2002

Filed:

Mar 5, 1999

Appl. No.:

09/263668

Inventors:

John Edward Derrick - Round Rock TX
Lee Evan Eisen - Austin TX
Paul Joseph Jordan - Austin TX
Robert William Hay - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

712204, 712 23

Abstract:

A method and system for aligning internal operations (IOPs) for dispatch are disclosed. The method and system comprise conditionally asserting a predecode based on a particular dispatch slot that an instruction is going to be placed. The method and system further include using the information related to the predecode to expand an instruction into at least one dummy operation and an IOP operation whenever the instruction would not be supported in the particular dispatch slot.

US Patent:

6430678, Aug 6, 2002

Filed:

Jul 29, 1999

Appl. No.:

09/363463

Inventors:

James Allan Kahle - Austin TX
Hung Qui Le - Austin TX
Lee Evan Eisen - Austin TX
John Edward Derrick - Round Rock TX
Robert William Hay - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 930

US Classification:

712217, 712244

Abstract:

An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.

US Patent:

6662360, Dec 9, 2003

Filed:

Sep 27, 1999

Appl. No.:

09/407105

Inventors:

Robert William Hay - Austin TX
James Allan Kahle - Austin TX
Brian R. Konigsburg - Austin TX
David Stephen Levitan - Austin TX
Balaram Sinharoy - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 944

US Classification:

717131, 717154, 712239

Abstract:

A method and system is disclosed for software manipulation of hardware prediction mechanism in a data processor with software prediction. The hardware branch prediction mechanism is enhanced with at least two bits for path prediction. These bits are settable by a software and are capable of overriding the hardware branch prediction mechanism. Branch prediction information is encoded into a branch instruction in the software. This information includes a pre-determined value for each bit. Finally, a branch path of said instruction is predicted based on the value of the bits.

US Patent:

6823447, Nov 23, 2004

Filed:

Mar 1, 2001

Appl. No.:

09/798166

Inventors:

Robert William Hay - Austin TX
Balaram Sinharoy - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

712239, 712237

Abstract:

A field is defined in branch instructions which is interpreted by software as âHintâ bits and these bits are used to signal the processor of special circumstances that may arise when doing speculative branch instruction execution to enable better branch address prediction accuracy and a reduction in link stack corruption which improves overall execution times. A programmer or compiler determines if a branch instruction usage fits in the context for a Hint action. If so, the compiler or programmer, using assembly/machine language, sets Hint bits in the branch instruction when it is compiled. If the branch is later speculatively executed, the processor decodes the Hint bits and executes and a hardware action corresponding the decode of the Hint bits. These Hints include four specific Hint actions, however, the field reserved for Hint bits is five bit wide reserving up to thirty-two specific Hint cases may be specified. These Hint cases (or Hint bits) may be interpreted differently for each type of branch instruction supported.