Robert Daniel Heath

US Patent:

7246267, Jul 17, 2007

Filed:

Sep 30, 2002

Appl. No.:

10/262227

Inventors:

David L. Bennett - Aloha OR, US
Robert J. Heath - Aloha OR, US
Mark L. Millard - Portland OR, US

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

G06F 11/00

US Classification:

714 39, 714 49, 714 51, 717125, 717127

Abstract:

A logic analyzer according to the subject invention includes a disassembler for disassembling object code. The disassembler automates the process of locating op-code addresses by utilizing information derived from an object file corresponding to the code whose execution is being disassembled. The object file includes addresses for the starting location of op-codes corresponding to individual source code lines. When the disassembler cannot determine the correct starting location for an op-code, it uses information from the object file to obtain the address of an op-code within a specified range of interest.

US Patent:

7369604, May 6, 2008

Filed:

Sep 27, 2002

Appl. No.:

10/259372

Inventors:

Robert J. Heath - Aloha OR, US

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

H04B 3/46

US Classification:

375224, 702 66, 702 70, 702187

Abstract:

Apparatus according to the subject invention includes two independent acquisition systems, wherein one of the two independent acquisition systems acquires the acquisition clock of the other acquisition system along with a signal from a known acquisition reference point. In general, the first independent acquisition system is a logic analyzer, and the second independent acquisition system can be an ILA, a second logic analyzer, an oscilloscope, or other sampling device.

US Patent:

7634747, Dec 15, 2009

Filed:

May 17, 2007

Appl. No.:

11/749897

Inventors:

Michael S. Hagen - Vancouver WA, US
Robert J. Heath - Aloha OR, US
Glenn R. Johnson - Aloha OR, US
Kenneth R. Marti - Portland OR, US
James M. Fenton - Tigard OR, US
Jonathan D. Clem - Hillsboro OR, US

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

G06F 17/50
G06F 9/45
G01B 11/16

US Classification:

716 4, 716 6, 356 32

Abstract:

A method of trace delay error compensation for measurements that are taken remotely from the signal source or receiver of a circuit uses data available from a computer aided design (CAD) tool to characterize electrical connections to an instrument measurement point, such as a connectorless probe, which is remote from the signal source or receiver. Extracted parameters from the CAD data are applied to signals acquired by the probe to adjust the signal timing and/or shape to more accurately represent the signal information timing at the signal source or receiver or other remote location of interest to a user. The corrected signals at the desired location may be displayed by a measurement instrument.

US Patent:

60165561, Jan 18, 2000

Filed:

Jul 17, 1997

Appl. No.:

8/895544

Inventors:

Robert J. Heath - Aloha OR

Assignee:

Tektronix, Inc. - Wilsonville OR

International Classification:

G06F 1100

US Classification:

714 38

Abstract:

A system and method for locating a data sample in a logic analyzer or emulator acquisition buffer corresponding to a source code statement employs first and second windows, wherein one window displays the contents of the acquisition buffer, for example, in disassembly form and the other window displays source code. When a source code file is displayed and a specified statement is selected within the source code, a search for a matching sample in the acquisition buffer is initiated. If a sample is found, it is displayed and highlighted in the appropriate window.