Robert A Howell

US Patent:

7020867, Mar 28, 2006

Filed:

Mar 22, 2002

Appl. No.:

10/104997

Inventors:

Mark Underseth - Carlsbad CA, US
Hugues Valois - San Diego CA, US
Robert Howell - San Diego CA, US

Assignee:

S2 Technologies, Inc. - Cardiff CA

International Classification:

G06F 9/44

US Classification:

717106, 717121, 719314

Abstract:

A system and method for providing seamless communication with threads executing on an embedded computer. Using a DAT system, a programmer can test the communication interfaces of a thread via either a scripting program, any COM-compliant program, or a graphical test utility. The DAT system automatically formats a block of data that is transmitted between the embedded computer and a host computer and accounts for machine specific enumeration sizes, machine specific pointer sizes, machine specific structure alignment boundaries, machine specific integer sizes, and machine specific byte ordering.

US Patent:

7237230, Jun 26, 2007

Filed:

Mar 22, 2002

Appl. No.:

10/105069

Inventors:

Mark Underseth - Carlsbad CA, US
Kirk Fertitta - San Diego CA, US
Robert Howell - San Diego CA, US

Assignee:

S2 Technologies, Inc. - Cardiff CA

International Classification:

G06F 9/44

US Classification:

717127, 717124, 717131

Abstract:

A system and method for providing seamless communication with threads executing on an embedded computer. Using a DAT system, a programmer can test the communication interfaces of a thread via either a scripting program, any COM-compliant program, or a graphical test utility. The DAT system automatically formats a block of data that is transmitted between the embedded computer and a host computer and accounts for machine specific enumeration sizes, machine specific pointer sizes, machine specific structure alignment boundaries, machine specific integer sizes, and machine specific byte ordering.

US Patent:

7514301, Apr 7, 2009

Filed:

Sep 21, 2006

Appl. No.:

11/524246

Inventors:

Garrett A. Storaska - Reston VA, US
Robert S. Howell - Wheaton MD, US

Assignee:

Northrop Grumman Corporation - Los Angeles CA

International Classification:

H01L 21/00
H01L 21/84

US Classification:

438149

Abstract:

A method for fabricating nanocoils and improved nanocoils fabricated therefrom. Embodiments of the method utilizing deep reactive ion etching (DRIE). A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer, in which SOI wafer includes buried oxide layer, patterning one or more devices into a layer of silicon on top of the buried oxide layer, depositing tensile stressed nitride layer on the top silicon layer, patterning coiling arm structure on top silicon layer, patterning an overlapping etch window mask on bottom side of SOI wafer using, in which patterning overlapping etch window mask removes SOI wafer and exposes buried oxide layer in width greater than coiling arm structure, and releasing coiling arm structure so that coiling arm coils to form nanocoil. In embodiments, DRIE is utilized to pattern the overlapping etch window mask.

US Patent:

7601620, Oct 13, 2009

Filed:

Sep 21, 2006

Appl. No.:

11/524244

Inventors:

Garrett A. Storaska - Reston VA, US
Robert S. Howell - Wheaton MD, US

Assignee:

Northrop Grumman Systems Corporation - Los Angeles CA

International Classification:

H01L 21/00

US Classification:

438517, 438479, 216 2, 257E2132

Abstract:

Improved nanocoils, systems and methods for fabricating nanocoils. Embodiments enable wet etching techniques for releasing coiling arm structures and forming nanocoils. A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer in which SOI wafer includes a buried oxide layer, patterning one or more devices onto a silicon device layer on top of the buried oxide layer, depositing a tensile stressed layer on the silicon device layer so that stressed layer and silicon device layer form a stressed coiling bi-layer, patterning a coiling arm structure on the stressed coiling bi-layer, depositing a metal encapsulation layer on the stressed coiling bi-layer, and releasing the coiling arm structure so that coiling arm coils to form nanocoil. A system for fabricating nanocoils includes a substrate, a coiling arm structure including, a buried oxide layer deposited on the substrate, a stressed coiling bi-layer attached to the buried oxide layer including a silicon device layer that includes one or more devices defined thereon and a stressed nitride layer that provides a tensile coiling stress, and a metal encapsulation layer that protects stressed nitride layer from hydrofluoric (HF) acid used to release the coiling arm structure from the substrate during the wet etch technique so that coiling arm structure coils into nanocoil when released. Improved nanocoils may be fabricated according to these and other methods and systems.

US Patent:

7710235, May 4, 2010

Filed:

Sep 21, 2006

Appl. No.:

11/524245

Inventors:

Garrett A. Storaska - Reston VA, US
Robert S. Howell - Wheaton MD, US

Assignee:

Northrop Grumman Systems Corporation - Los Angeles CA

International Classification:

H01F 21/04
H01F 27/28

US Classification:

336225, 336 65, 336117, 336121, 336122, 385 18, 3592241

Abstract:

Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include inductors or traveling wave tubes fabricated from spiral nanocoils. Such applications includes inductors or traveling wave tubes fabricated from a method for fabricating nanocoils with a desired pitch. Such a method includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed.

US Patent:

7795647, Sep 14, 2010

Filed:

Mar 29, 2007

Appl. No.:

11/727955

Inventors:

Garrett A. Storaska - Reston VA, US
Robert S. Howell - Wheaton MD, US
Harvey C. Nathanson - Pittsburgh PA, US
Francis William Hopwood - Severna Park MD, US

Assignee:

Northrop Grumman Systems Corporation - Los Angeles CA

International Classification:

H01L 29/76

US Classification:

257213, 257401

Abstract:

A curled transistor comprises a coiled semiconductor substrate having a plurality of concentrically curled layers. Source and drain regions are configured on a portion of the coiled semiconductor substrate, and a gate dielectric is positioned between the source and drain regions. A first set of metallic contacts electrically couple to the source region on the coiled semiconductor substrate and a second set of metallic contacts electrically couple to the drain region on the coiled semiconductor substrate.

US Patent:

20060138604, Jun 29, 2006

Filed:

Dec 27, 2004

Appl. No.:

11/020270

Inventors:

Christopher Kirby - Gambrills MD, US
Robert Horner - Severn MD, US
Harlan Cramer - Columbia MD, US
Robert Howell - Silver Spring MD, US
Robert Tranchini - Ellicott City MD, US
Gregory DeSalvo - Joppa MD, US
Gilbert Dix - Annapolis MD, US
Jeremiah Horner - Glen Burnie MD, US

Assignee:

NORTHROP GRUMMAN CORPORATION - Los Angles CA

International Classification:

H01L 23/58

US Classification:

257640000

Abstract:

An improved dielectric suitable for use in electronic and micro-electromechanical (MEMS) components. The dielectric includes silicon nitride having a percentage of Si:H bonds greater than a percentage of N:H bonds, in order to reduce the level of charge trapping of the silicon nitride.

US Patent:

20060179427, Aug 10, 2006

Filed:

Mar 28, 2006

Appl. No.:

11/391026

Inventors:

Mark Underseth - Carlsbad CA, US
Hugues Valois - San Diego CA, US
Robert Howell - San Diego CA, US

International Classification:

G06F 9/45
G06F 9/44

US Classification:

717140000, 717106000

Abstract:

A system and method for providing seamless communication with threads executing on an embedded computer. Using a DAT system, a programmer can test the communication interfaces of a thread via either a scripting program, any COM-compliant program, or a graphical test utility. The DAT system automatically formats a block of data that is transmitted between the embedded computer and a host computer and accounts for machine specific enumeration sizes, machine specific pointer sizes, machine specific structure alignment boundaries, machine specific integer sizes, and machine specific byte ordering.