Robert H Huntington

US Patent:

40669190, Jan 3, 1978

Filed:

Apr 1, 1976

Appl. No.:

5/672682

Inventors:

Robert Charles Huntington - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 2702

US Classification:

307353

Abstract:

An electronic circuit suitable to be fabricated in monolithic integrated circuit form for producing at an output terminal an output signal for a predetermined time period of which the value thereof corresponds to the value of a periodically sampled, time varying, input signal applied at an input terminal. The circuit comprises two identical and parallel channels connected between the input and the output terminals such that one channel is in a sample mode while the other channel is in a hold mode and vice versa. Each channel includes a pair of operational amplifiers operatively coupled to an integrating capacitor. The dual channel system provides self compensation for offset voltage and common mode rejection. Thus, no manual nulling adjustment is required. Because self compensation is renewed each sample/hold cycle, the circuit is substantially insensitive to temperature variations over a broad range of temperatures.

US Patent:

40718301, Jan 31, 1978

Filed:

Jul 3, 1975

Appl. No.:

5/593073

Inventors:

Robert Charles Huntington - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 316

US Classification:

330277

Abstract:

A linear voltage amplifier includes an input stage which has a P channel MOSFET load device and an N channel input device. The complementary amplifier also includes a feedback circuit which includes a low pass filter coupled between the output stage and the gate electrode of the P channel load device. The P type tub region in which the N channel input MOSFET is located is biased by an adjustable bias circuit to control threshold voltage of the input MOSFET and thereby control the DC level of the output of the complementary amplifier. In one embodiment the biasing circuit includes a P channel MOSFET coupled in series with a diode connected N channel MOSFET between two voltage supply conductors, the gate of the P channel MOSFET being connected to the gate of the P channel MOSFET load device of the input stage. The junction between the P channel MOSFET and the diode connected N channel MOSFET is coupled to one terminal of a high value resistor, the other end of which is connected to the input conductor which is connected to the gate of the N channel input MOSFET.

US Patent:

42297303, Oct 21, 1980

Filed:

Jan 29, 1979

Appl. No.:

6/007064

Inventors:

Robert C. Huntington - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1320

US Classification:

340347NT

Abstract:

A method and an apparatus are disclosed for converting an analog input signal having either a positive or negative polarity into a digital output signal indicating the magnitude and polarity of the input signal. Amplifier offset voltages and dynamic hysteresis in the comparator are compensated automatically and a zero reference is established automatically to provide a corrected output. A compensation capacitor and an integrating capacitor are selectively charged. A reference signal is integrated to measure the magnitude of the difference between the integrator offset voltage and the comparator threshold. A digital representation of the time required to measure the difference between the integrator offset voltage and the comparator threshold is stored. The compensation capacitor and the integrating capacitor are again selectively charged. The analog input signal is then integrated for a fixed time.

US Patent:

44737580, Sep 25, 1984

Filed:

Feb 7, 1983

Appl. No.:

6/464163

Inventors:

Robert C. Huntington - Phoenix AZ

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H03K 1716
H03K 17693
H03K 19094

US Classification:

307296R

Abstract:

An integrated circuit and method includes a substrate bias voltage control circuit formed on a common substrate therewith for ensuring that the substrate has a voltage applied thereto while a semiconductor device on the substrate has a supply voltage applied thereto which includes means for providing sources of bias and supply voltages to the substrate with means for firstly coupling the bias voltage to the substrate when the bias voltage is present and means for secondly coupling the supply voltage to the substrate when the bias voltage is not present.

US Patent:

41076710, Aug 15, 1978

Filed:

Sep 1, 1976

Appl. No.:

5/719550

Inventors:

Robert Charles Huntington - Phoenix AZ
James Everett Cooper - Woodland Hills CA

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1302

US Classification:

340347DA

Abstract:

An apparatus and method are disclosed for converting digital input signals of either polarity to representative analog output signals. An internal synchronous counter is clocked to generate internal digital signals of the same code as the input digital signal which are compared with the input digital signal which is stored in a bank of latches. Upon coincidence therebetween, an inhibiting pulse is produced from a coincidence circuit for disabling a buffer-integrator circuit. During the time interval between the enabling of the counter and the inhibiting pulse, the buffer-integrator integrates a single polarity reference voltage provided thereto to establish an analog voltage representative of the stored digital signal. Sample and hold circuits periodically sample the output of the integrator circuit to update and provide the analog output. Self compensation for operational amplifier offsets is provided during each conversion cycle.

US Patent:

47852003, Nov 15, 1988

Filed:

Aug 20, 1987

Appl. No.:

7/056171

Inventors:

Robert C. Huntington - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 3037
H03K 3356

US Classification:

307279

Abstract:

A self correcting single event upset-hardened CMOS register comprises a master portion and a slave portion. The master portion is coupled to a source of data and includes a feedback means such that said master portion can store said data during the first phase of a bi-phase clock signal. A slave portion including a second feedback path, has an input coupled to the output of said master portion and has an output which comprises the output of the register. An odd plurality of inverters is placed in series in the feedback path so as to isolate each node which is a possible site for high-energy particle impingement from other nodes in the loop and to attenuate and delay any resulting impulses such that the state of the error pulse cannot be maintained thus permitting the slave loop to remain in the state determined by the preceding data pulse.

US Patent:

46755578, Jun 23, 1987

Filed:

Mar 20, 1986

Appl. No.:

6/841977

Inventors:

Robert C. Huntington - Phoenix AZ

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H03K 19092
H03K 301
H03K 3353
H01L 902

US Classification:

307475

Abstract:

A voltage translator circuit is provided to reduce a supply voltage to a lower, predetermined, relatively constant and unconditionally stable operating voltage without the use of external components. A voltage divider comprising a plurality of series connected CMOS FETs located in P-regions, is used to establish an operating voltage. Additional CMOS FETs are used to supply the load current and control the no-load voltage.