Robert R Jarrett

US Patent:

43486002, Sep 7, 1982

Filed:

Mar 21, 1980

Appl. No.:

6/132704

Inventors:

Robert B. Jarrett - Tempe AZ
Wilson D. Pace - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 19081
H01L 2704

US Classification:

307475

Abstract:

Structure fabricating using standard integrated injection logic (I. sup. 2 L) process techniques for providing a multiple of controlled current source outputs for driving I. sup. 2 L to analog interfaces. The current source structure is formed in minimum die area because of the space saving features of I. sup. 2 L and tracks the performance of the I. sup. 2 L circuit. The current source includes a common P-type emitter region diffused into an isolated N-type epitaxial layer which has been isolated by a deep N+-type diffusion region. Multiple collector P-type regions which are isolated from each other by the N+-type isolating region are diffused into the isolated portion of the epitaxial layer in spaced relationship to the common emitter region. An ion implanted resistor couples the common emitter region to a source of operating potential such that current is injected from the emitter region via the lateral PNP formed transistors to produce multiple output currents from the collector regions. The collector regions are connected using conductive interconnects to respective I. sup.

US Patent:

49704125, Nov 13, 1990

Filed:

Jul 28, 1989

Appl. No.:

7/386063

Inventors:

Robert B. Jarrett - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 5153

US Classification:

307363

Abstract:

A comparator circuit with hysteresis does not require any bias current as long as the input signal applied thereto is less than a lower threshold value of the comparator. The comparator includes a current source for providing a plurality of currents when enabled, a Zener diode coupled to the current source for initially enabling the former as the input signal exceeds an upper threshold value, an output circuit which when rendered operative is placed in parallel to the Zener and disables the same while maintaining the current source enabled and providing an output signal from the comparator, and an amplifier responsive to the current source which renders the output circuit operative as the magnitude of current sourced thereto exceeds a predetermined value. A feature of the comparator circuit is that the currents flowing in the output circuit and amplifier have complementary temperature coefficients whereby the composite temperature coefficient of the upper and lower threshold values of the comparator can be adjusted to have a substantially zero temperature coefficient.

US Patent:

50087363, Apr 16, 1991

Filed:

Nov 20, 1989

Appl. No.:

7/438382

Inventors:

Robert B. Davies - Tempe AZ
Robert B. Jarrett - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2336

US Classification:

357 75

Abstract:

A thermally protected power transistor comprising a first chip which includes a power transistor and a second chip which includes protection circuitry. The second chip has a plurality of metallic bumps formed thereon which are coupled to various portions of the protection circuitry, wherein at least one metallic bump serves as a thermal couple. The protection circuitry chip is mounted upside down on the power transistor chip and coupled to the power transistor chip by the metallic bumps. The metallic bumps serve to provide electrical power for the protection circuitry, to couple control signals between the protection circuitry and the power transistor, and to couple thermal information from the power transistor to the protection circuitry.

US Patent:

41212738, Oct 17, 1978

Filed:

Jan 14, 1977

Appl. No.:

5/759516

Inventors:

Robert Benjamin Jarrett - Tempe AZ
Wilson David Pace - Tempe AZ
Howard Fredrick Weber - Scottsdale AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

B60K 3100

US Classification:

361239

Abstract:

A cruise control system having means to provide a signal corresponding to a desired speed for use by a servo control to regulate the speed. This system uses a current source to ramp charge a first capacitor. A comparator compares magnitude of the voltage on the first capacitor against the signal representative of the desired speed. A first counter is used to accumulate counts from a first frequency generator. A latch counter capable of following the counts in the first counter is used to store the counts when the comparator indicates the voltage on the first capacitor is substantially equal to the magnitude of the signal representative of the speed. A digital comparator then compares the counts stored in the latch counter against counts being accumulated anew in the first counter while the first capacitor is being recharged. Means are provided to inhibit the first capacitor from being charged further after the digital comparator indicates equality between the quantity of the counts being compared. Means to transfer the voltage on the first capacitor to a second capacitor are used so that the voltage on the second capacitor can be compared against the signal representative of the actual speed which then provides an output to the servo control to regulate the speed.

US Patent:

43586899, Nov 9, 1982

Filed:

Jul 7, 1980

Appl. No.:

6/166864

Inventors:

Robert B. Jarrett - Tempe AZ
James J. LoCascio - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 508
H03K 5153
H03K 19092

US Classification:

307264

Abstract:

An interface circuit adapted to receive an analog input signal for generating first and second output signals at respective outputs in response to the input signal varying above a first reference voltage level and varying below a second reference voltage level. The interface circuit comprising first and second circuits each of which has an input coupled to the input of the interface circuit and receiving the first and second reference voltage levels respectively. Each one of the two circuits includes a voltage translation circuit for translating the reference voltage level supplied thereto and a comparator to produce the particular output signal in response to the input signal level assuming the aforementioned relationship with respect to the respective two reference voltage levels.

US Patent:

45673888, Jan 28, 1986

Filed:

Oct 3, 1983

Appl. No.:

6/538241

Inventors:

Robert B. Jarrett - Tempe AZ
W. Eric Main - Mesa AZ
Robert A. Neidorff - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 508

US Classification:

307540

Abstract:

This relates to a circuit for clamping the voltage across first and second terminals (in this case the gate and source electrodes of a power MOSFET) in response to the receipt of a signal indicating a load fault. An input turnaround transistor receives the signal indicative of the fault and generates a current in response thereto which is applied to the base of a switching transistor. When this current exceeds a predetermined value, the switching transistor turns on which in turn causes a buffer circuit including a PNP transistor to turn on. When the buffer circuit turns on, current is drawn through a zener diode which is coupled to the second terminal. Thus, the clamping circuit between the gate and source terminals equals the voltage drop across the zener diode plus that dropped across the buffer circuit plus the saturation voltage of the switching transistor. Resistors are provided in the buffer circuit to provide for a certain amount of adjustment of the clamping voltage.

US Patent:

43396690, Jul 13, 1982

Filed:

Jul 8, 1980

Appl. No.:

6/166866

Inventors:

Robert B. Jarrett - Tempe AZ
James J. LoCascio - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 508

US Classification:

307228

Abstract:

A circuit responsive to a supplied control input signal for alternately sourcing and sinking current at an output the values of which are accurately matched comprising a single current reference source and a single NPN current mirror circuit. The current reference source is unilaterally coupled to the output when the circuit is in a first mode of operation to provide the source current and is coupled to the NPN current mirror circuit which is rendered conductive in a second mode of operation to provide the input current to said current mirror. The output of the current mirror being coupled to the output sinks current thereat which is substantially equal to the input current supplied thereto. The NPN current mirrors comprises a pair of matched transistors having the bases and emitters interconnected at first and second nodes respectively. The collector of the first one of the matched transistors is coupled to the current reference source with the collector of the second transistor being coupled to the output of the circuit.

US Patent:

43365078, Jun 22, 1982

Filed:

Jan 29, 1981

Appl. No.:

6/229485

Inventors:

Byron G. Bynum - Tempe AZ
Robert B. Jarrett - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 3282

US Classification:

331108D

Abstract:

An integrated circuit current-output relaxation oscillator utilizes an internal or external capacitor which is alternately charged from +V. sub. BE to a predetermined upper trip point and then discharged to +V. sub. BE. A control current proportional to the voltage across the capacitor is generated and compared with a reference current. When the control current achieves a predetermined value with respect to the reference current, a transistor is turned on permitting the capacitor to discharge to +V. sub. BE. The control current is generated by the same current mirror circuit which generates the oscillating output current and is either equal or proportional thereto. Therefore, the magnitude of the oscillating output current is dominantly proportional to the magnitude of the reference current, and the frequency of oscillation is dominantly dependent on passive components; i. e. a resistor and a capacitor.