Robert A Jarvela

US Patent:

40005097, Dec 28, 1976

Filed:

Mar 31, 1975

Appl. No.:

5/563550

Inventors:

Robert A. Jarvela - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2302
H01L 2342
H01L 3902
H01L 2504

US Classification:

357 81

Abstract:

A high density low profile air cooled wafer package including flip chip and embedded logic or memory islands upon a wafer package mounted within a heat dissipating cover having improved thermal dissipation. Heat dissipation is achieved through a thermal grease interface provided between the wafer carrier and the heatsink cover, with pressure being applied to the interface by partially deflected electrical connectors secured there between.

US Patent:

46284117, Dec 9, 1986

Filed:

May 2, 1985

Appl. No.:

6/729831

Inventors:

Demetrios Balderes - Wappingers Falls NY
Andrew J. Frankovsky - Endwell NY
Robert A. Jarvela - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 500

US Classification:

361414

Abstract:

A direct module powering scheme is disclosed. A plurality of integrated circuit chips are mounted on a module. The module is mounted on a printed circuit board. A plurality of metallization layers are distributed in parallel fashion within the module. A voltage tab is mounted on the edge of the module substrate and in contact with the edge of the metallization layers. The voltage tab may be attached to a source of power for providing the necessary voltage and current to the module needed to power the chips mounted on the module. The metallization layers comprise voltage distribution layers and voltage reference (ground) layers. The voltage tab is connected to the edge of the voltage distribution layer. A plurality of plated vias are disposed through the module in contact with one or more of the metallization layers. A plurality of voltage distribution stripes are disposed on the bottom of the module substrate and in contact with the plated vias for providing the necessary voltage and current to remotely-located chips, relative to the voltage tab, needed to power the chips.