Robert K Kong

US Patent:

46672931, May 19, 1987

Filed:

Aug 27, 1984

Appl. No.:

6/644872

Inventors:

Charles F. Krieger - Danville CA
Wilbur L. Schultz - Kensington CA
Robert L. Kong - San Francisco CA

Assignee:

Computer Election Systems - Berkeley CA

International Classification:

G06F 1520
G06G 748
G09G 302

US Classification:

364409

Abstract:

A method and apparatus for selecting one of a multiplicity of preidentified items, such as candidates on an election ballot. Each item has an associated light emitting element which has an on/off status. The use of the lights is time multiplexed between status display and item selection tasks. For at least a first certain portion of each of a plurality of successive time cycles, the lights with an on status are energized. The lights which are energized are associated with previously selected items. They are energized to a level of illumination visible to the human eye in a normal ambient light environment. For a second portion of each time cycle, a multiplicity of the lights are energized in a prearranged time dependent algorithmic pattern. During this portion of the time cycle the lights are energized only to a level of illumination not normally visible to the human eye in a normal ambient light environment. Items are selected by positioning a light detection element sufficiently close to the item's associated light to receive the light emitted therefrom during at least one of the second portions of the time cycles.

US Patent:

20200350919, Nov 5, 2020

Filed:

May 2, 2019

Appl. No.:

16/401737

Inventors:

- Cupertino CA, US
Feng Zhao - San Jose CA, US
Wei Deng - San Jose CA, US
Chunwei Chang - San Jose CA, US
Robert K. Kong - San Francisco CA, US
Saeed Chehrazi - Irvine CA, US

International Classification:

H03L 7/18
H03L 7/089
H03L 7/093
H03L 7/099

Abstract:

In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.