Robert Vincent Lazaravich

US Patent:

7532027, May 12, 2009

Filed:

Sep 28, 2007

Appl. No.:

11/864625

Inventors:

Robert Lazaravich - Chandler AZ, US
Hugh Littlebury - Gilbert AZ, US

Assignee:

Adtron, Inc. - Phoenix AZ

International Classification:

H03K 19/00

US Classification:

326 8, 326 37

Abstract:

A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device.

US Patent:

7804319, Sep 28, 2010

Filed:

Mar 31, 2009

Appl. No.:

12/415549

Inventors:

Robert Lazaravich - Chandler AZ, US
Hugh Littlebury - Gilbert AZ, US

Assignee:

Adtron Corporation - Phoenix AZ

International Classification:

H03K 19/00

US Classification:

326 8, 326 37

Abstract:

A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device.

US Patent:

8149012, Apr 3, 2012

Filed:

Sep 24, 2010

Appl. No.:

12/890436

Inventors:

Robert Lazaravich - Chandler AZ, US
Hugh Littlebury - Gilbert AZ, US
Robert William Ellis - Phoenix AZ, US

Assignee:

SMART Storage Systems, Inc. - Chandler AZ

International Classification:

H03K 19/00

US Classification:

326 8, 326 37

Abstract:

A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device.

US Patent:

55242235, Jun 4, 1996

Filed:

Jun 12, 1995

Appl. No.:

8/489241

Inventors:

Robert V. Lazaravich - Chandler AZ
Jill L. Kuester - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 940

US Classification:

395375

Abstract:

An instruction accelerator which includes an instruction source, and a single instruction multiple data array processor which executes the instructions supplied by the instruction source. A loop processor identifies all loop type instructions which are supplied by the instruction source, copies those instructions supplied by the instruction source into a loop memory, and supplies those loop instructions to the single instruction multiple data array processor in the order received, at the rate required by the single instruction multiple data array processor, and as many times as required by the loop count field.

US Patent:

20170026043, Jan 26, 2017

Filed:

Jul 22, 2016

Appl. No.:

15/217294

Inventors:

- Chelmsford MA, US
Robert V. Lazaravich - Chandler AZ, US

Assignee:

Mercury Systems, Inc. - Chelmsford MA

International Classification:

H03K 19/0185
H03K 5/08

Abstract:

Various systems may benefit from interfaces for handling multiple types of inputs. For example, a device with a trigger input from an external device may benefit from an isolated logic level trigger that is capable of addressing multiple types and values of voltage. An apparatus can include an input configured to receive an external trigger input signal having a trigger input voltage. The apparatus can also include circuitry configured to automatically adjust the trigger input voltage to a value configured to be compatible with a provided attached system. A working range of the trigger input voltage can exceed a compatible working range of the provided attached system.

US Patent:

20150156020, Jun 4, 2015

Filed:

Dec 2, 2014

Appl. No.:

14/557729

Inventors:

- Aliso Viejo CA, US
Robert V. Lazaravich - Chandler AZ, US
Sabrina S. Pina - Phoenix AZ, US
Kenneth R. Paxman - Chandler AZ, US
Rudolph J. Sterbenz - Chandler AZ, US

International Classification:

H04L 9/08

Abstract:

Various storage devices may benefit from encryption technologies. For example, storage devices may benefit from systems and methods for a fully isolated encryption key filling port. A system can, for example, include a host connector installed in a host computer and configured to connect to a storage connector in a storage device. The system can also include a key fill device connected to the host connector. The key fill device may be configured to communicate data to the storage device via one or more pins in the host connector. The host computer may be configured to not use the one or more pins as data pins.

US Patent:

20150100795, Apr 9, 2015

Filed:

Oct 7, 2014

Appl. No.:

14/508655

Inventors:

- Aliso Viejo CA, US
Sabrina S. Pina - Phoenix AZ, US
Rudolph J. Sterbenz - Chandler AZ, US
Kenneth R. Paxman - Chandler AZ, US
Robert V. Lazaravich - Chandler AZ, US

International Classification:

G06F 21/82

US Classification:

713193

Abstract:

Various devices may benefit from enhanced security. For example, secure storage devices and authentication devices may benefit from security that permits isolation of the devices from the operating system and data ports of a host computer. An apparatus can include a first interface configured to connect to a non-volatile storage device. The apparatus can also include circuitry configured to supply an encryption key over the first interface to decrypt data on the non-volatile storage device. The first interface is configured to connect directly to the non-volatile storage device.